Sylpheed/tools/ppc-manual/control/crand.md

crand — Condition Register AND

Category: Control / CR / SPR · Form: XL · Opcode: 0x4c000202

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
crand	crand	—	Condition Register AND

Syntax

crand [CRBD], [CRBA], [CRBB]

Encoding

crand — form XL

• Opcode word: 0x4c000202
• Primary opcode (bits 0–5): 19
• Extended opcode: 257
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (19)
6–10	BT/BO	target / branch options
11–15	BA/BI	source A / CR bit to test
16–20	BB	source B
21–30	XO	extended opcode (10 bits)
31	LK	link flag

Operands

Field	Role	Description
CRBA	crand: read	CR source bit A (0–31).
CRBB	crand: read	CR source bit B (0–31).
CRBD	crand: write	CR destination bit (0–31).

Register Effects

crand

• Reads (always): CRBA, CRBB
• Reads (conditional): none
• Writes (always): CRBD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

crand

• Canary XML: tools/ppc-instructions.xml — search for mnem="crand"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_control.cc:352
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:35
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:832

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_crand(PPCHIRBuilder& f, const InstrData& i) {
  // CR[bt] <- CR[ba] & CR[bb]   bt=bo, ba=bi, bb=bb
  Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
  Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
  Value* bt = f.And(ba, bb);
  f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
  return 0;
}

Special Cases & Edge Conditions

• Bit-level granularity. All eight CR-logical instructions operate on single CR bits, not whole 4-bit fields. CRBD, CRBA, CRBB are 5-bit absolute indices into the 32-bit CR register: BI = 4·field + bit-within-field, where bit 0 = LT, 1 = GT, 2 = EQ, 3 = SO.
• Operation. CR[CRBD] ← CR[CRBA] AND CR[CRBB]. All other CR bits are preserved.
• Same-source / same-destination quirks. Identical sources and destinations are legal: crand 6, 6, 6 is a NOP-style "force CR bit 6 to itself"; crand bt, bt, bt reads-then-writes the same bit (no observable change). Compilers exploit crxor BT,BT,BT ("clear bit") and creqv BT,BT,BT ("set bit") for similar tricks — see those pages.
• Combining branch conditions. The classic use: synthesise complex branch conditions from multiple compare results. Example: cmpw cr0, r3, r4; cmpw cr1, r5, r6; crand 4*cr0+2, 4*cr0+2, 4*cr1+2; beq cr0, label branches if r3==r4 AND r5==r6 using a single conditional branch.
• No Rc / OE. XL-form CR-logical ops never set CR0 or XER; they only update the named CR bit.
• Not synchronising. Pure data-flow on CR; freely reorderable.
• xenia status. xenia-rs decodes crand (decoder slot 540) but the interpreter snapshot is not embedded on this page — implementation lives in crates/xenia-cpu/src/interpreter.rs. xenia-canary's InstrEmit_crand emits the equivalent host AND of the two CR bits.

Related Instructions

• crandc — AND with complement: CR[BT] ← CR[BA] AND ¬CR[BB].
• cror, crorc — OR / OR-with-complement.
• crnand, crnor — negated AND / OR.
• crxor, creqv — XOR and equivalence (XNOR).
• mcrf — copy a whole 4-bit CR field.
• bcx consumers — the typical reason to compute composite CR bits.

Simplified Mnemonics

• crmove BT, BA ≡ cror BT, BA, BA (use cror, not crand).
• crset BT ≡ creqv BT, BT, BT (set to 1).
• crclr BT ≡ crxor BT, BT, BT (clear to 0).

crand itself has no dedicated simplified mnemonic.

IBM Reference

• AIX 7.3 — crand (Condition Register AND)
• AIX 7.3 — Condition register simplified mnemonics