Files

sim 9bfe96e44d fix(ppc-manual): 543 dead links, from two generator bugs and wrong relative paths

- Category pages linked each family as `<slug>.md`, relative to categories/,
  where no family page lives. They now link `../<category>/<slug>.md`.
- Form pages linked a member into its *own* category directory, so every
  VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is
  under vmx/. They now link into the family's directory.
- Hand-written "Related" and sibling mentions linked other categories' pages
  as if they were in the same directory. 109 are retargeted through the page
  index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and
  6 naming instructions the manual has no page for are plain text now.

Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and
re-pinning belongs in its own change. The generator reports 0 family pages
changed and is idempotent; the only dead links left are TEMPLATE.md's
placeholders.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>

2026-09-16 22:37:12 +02:00

6.5 KiB

Raw Blame History

`vrfiz` — Vector Round to Floating-Point Integer toward Zero

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000024a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
`vrfiz`	`vrfiz`	—	Vector Round to Floating-Point Integer toward Zero
`vrfiz128`	`vrfiz128`	—	Vector128 Round to Floating-Point Integer toward Zero

Syntax

vrfiz [VD], [VB]
vrfiz128 [VD], [VB]

Encoding

`vrfiz` — form `VX`

Opcode word: 0x1000024a
Primary opcode (bits 0–5): 4
Extended opcode: 586
Synchronising: no

Bits	Field	Meaning
0–5	`OPCD`	primary opcode (4)
6–10	`VRT/VD`	destination vector register
11–15	`VRA/VA`	source A vector register
16–20	`VRB/VB`	source B vector register
21–31	`XO`	extended opcode (11 bits)

`vrfiz128` — form `VX128_3`

Opcode word: 0x180003f0
Primary opcode (bits 0–5): 6
Extended opcode: 1008
Synchronising: no

Bits	Field	Meaning
0–5	`OPCD`	primary opcode (6)
6–10	`VD128l`	destination low 5 bits
11–15	`IMM`	5-bit immediate
16–20	`VB128l`	source B low 5 bits
21–27	`XO`	extended opcode
28–29	`VD128h`	destination high 2 bits
30–31	`VB128h`	source B high 2 bits

Operands

Field	Role	Description
`VB`	vrfiz: read; vrfiz128: read	Source B vector register.
`VD`	vrfiz: write; vrfiz128: write	Destination vector register.

Register Effects

`vrfiz`

Reads (always): VB
Reads (conditional): none
Writes (always): VD
Writes (conditional): none

`vrfiz128`

Reads (always): VB
Reads (conditional): none
Writes (always): VD
Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vrfiz

Canary XML: tools/ppc-instructions.xml — search for mnem="vrfiz"
Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1255
Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:429
Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:601

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vrfiz(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrfiz_(f, i.VX.VD, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1249) ──
int InstrEmit_vrfiz_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- RndToFPInt32Trunc(VB)
  Value* v = f.Round(f.LoadVR(vb), ROUND_TO_ZERO);
  f.StoreVR(vd, v);
  return 0;
}

vrfiz128

Canary XML: tools/ppc-instructions.xml — search for mnem="vrfiz128"
Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1258
Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:430
Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:778

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vrfiz128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrfiz_(f, VX128_3_VD128, VX128_3_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1249) ──
int InstrEmit_vrfiz_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- RndToFPInt32Trunc(VB)
  Value* v = f.Round(f.LoadVR(vb), ROUND_TO_ZERO);
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

Round toward zero (truncate). Each 32-bit float lane of VB has its fractional part dropped. 3.7 → 3.0, −3.7 → −3.0.
IEEE-754 binary32 output; VSCR[NJ] honoured.
Integer-too-big lanes are no-ops.
NaN and ±∞ pass through.
No VSCR[SAT], no FPSCR update. vrfiz is the VMX analogue of C's truncf.
Big-endian lane indexing.
VMX128 sibling vrfiz128.

vrfin, vrfim, vrfip — the other three rounding modes.
vctsxs, vctuxs — float → signed / unsigned fixed-point (these truncate too, and also apply a UIMM power-of-two scale).

6.5 KiB Raw Blame History Unescape Escape

vrfiz — Vector Round to Floating-Point Integer toward Zero