Sylpheed/tools/ppc-manual/vmx/vrlw.md

vrlw — Vector Rotate Left Integer Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000084

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vrlw	vrlw	—	Vector Rotate Left Integer Word
vrlw128	vrlw128	—	Vector128 Rotate Left Word

Syntax

vrlw [VD], [VA], [VB]
vrlw128 [VD], [VA], [VB]

Encoding

vrlw — form VX

• Opcode word: 0x10000084
• Primary opcode (bits 0–5): 4
• Extended opcode: 132
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vrlw128 — form VX128

• Opcode word: 0x18000050
• Primary opcode (bits 0–5): 6
• Extended opcode: 80
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vrlw: read; vrlw128: read	Source A vector register.
VB	vrlw: read; vrlw128: read	Source B vector register.
VD	vrlw: write; vrlw128: write	Destination vector register.

Register Effects

vrlw

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vrlw128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vrlw

• Canary XML: tools/ppc-instructions.xml — search for mnem="vrlw"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1284
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:434
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:565

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vrlw(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrlw_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1278) ──
int InstrEmit_vrlw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD) <- ROTL((VA), (VB)&0x1F)
  Value* v = f.VectorRotateLeft(f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
  f.StoreVR(vd, v);
  return 0;
}

vrlw128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vrlw128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1287
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:435
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:807

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vrlw128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrlw_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1278) ──
int InstrEmit_vrlw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD) <- ROTL((VA), (VB)&0x1F)
  Value* v = f.VectorRotateLeft(f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Per-lane left-rotate of words. For each of the 4 word lanes, VD.w[i] = rotate_left(VA.w[i], VB.w[i] & 0x1F). Low 5 bits of each shift-count word are used.
• Per-lane shift counts. Splat with vspltw or vspltisw for uniform rotation.
• Big-endian word lanes. Lane 0 is the most significant 4 bytes.
• No overflow, no saturation.
• No Rc, no XER, no VSCR effect.
• VMX128 sibling vrlw128 — same op with the wider register file.
• Building block for vrlimi128. VMX128 fuses a rotate with an immediate-masked insert for cheaper bitfield shuffles; vrlw is the plain variant that the XDK uses for scalar-style 32-bit rotates.

Related Instructions

• vrlb, vrlh — byte / half-word rotate siblings.
• vslw, vsrw, vsraw — word shift-left / logical-right / arithmetic-right.
• vsl, vsr — bit-level whole-register shifts.
• vspltw, vspltisw — splat sources for uniform shift counts.
• vrlimi128 — rotate + mask-insert (VMX128-exclusive).

IBM Reference

• AIX 7.3 — vrlw (Vector Rotate Left Integer Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate