f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
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vmsum3fp128 — Vector128 Multiply Sum 3-way Floating Point
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
vmsum3fp128 |
vmsum3fp128 |
— | Vector128 Multiply Sum 3-way Floating Point |
Syntax
vmsum3fp128 [VD], [VA], [VB]
Encoding
vmsum3fp128 — form VX128
- Opcode word:
0x14000190 - Primary opcode (bits 0–5):
5 - Extended opcode:
400 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (4 or 5) |
| 6–10 | VD128l |
destination low 5 bits |
| 11–15 | VA128l |
source A low 5 bits |
| 16–20 | VB128l |
source B low 5 bits |
| 21 | VA128H |
source A high bit |
| 22 | — |
reserved |
| 23–25 | VC |
optional VC / XO sub-field |
| 26 | VA128h |
source A middle bit |
| 27 | — |
reserved |
| 28–29 | VD128h |
destination high 2 bits |
| 30–31 | VB128h |
source B high 2 bits |
Operands
| Field | Role | Description |
|---|---|---|
VA |
vmsum3fp128: read | Source A vector register. |
VB |
vmsum3fp128: read | Source B vector register. |
VD |
vmsum3fp128: write | Destination vector register. |
Register Effects
vmsum3fp128
- Reads (always):
VA,VB - Reads (conditional): none
- Writes (always):
VD - Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
C Translation Example
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
vmsum3fp128
- Canary XML:
tools/ppc-instructions.xml— search formnem="vmsum3fp128" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:1054 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:377 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:731
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_vmsum3fp128(PPCHIRBuilder& f, const InstrData& i) {
// Dot product XYZ.
// (VD.xyzw) = (VA.x * VB.x) + (VA.y * VB.y) + (VA.z * VB.z)
// chrispy: denormal outputs for Dot product are unconditionally made 0
Value* v = f.DotProduct3(f.LoadVR(VX128_VA128), f.LoadVR(VX128_VB128));
f.StoreVR(VX128_VD128, v);
return 0;
}
Special Cases & Edge Conditions
- 3-way float dot product. Computes
s = VA[0]*VB[0] + VA[1]*VB[1] + VA[2]*VB[2](ignoring lane 3 — the "w" component of a homogeneous vector) and broadcastssto every lane ofVD. Typical call site: 3D vector dot products where the w-component is padding. - Scalar-result-splatted-across-lanes. Consuming code can then use any lane of
VDas the dot-product result. - Rounding. Canary widens the lanes to binary64, multiplies and sums there, and rounds to binary32 once at the end (
vcvtsd2ss), so single-precision summation order does not come into it. Its emitter comment adds that denormal results are made 0 unconditionally. - IEEE-754 binary32;
VSCR[NJ]honoured. - No VSCR[SAT], no FPSCR update.
- VMX128 register-fusion (7-bit IDs on
VA,VB,VD). - No IBM AIX entry — Xenon-only.
- No
Rc, no XER.
Related Instructions
vmsum4fp128— 4-way dot-product (includes the w-lane).vmulfp128,vaddfp— the building blocks.vmaddcfp128,vmaddfp— fused MAC variants.vsumsws— integer sum-reduction analogue.
IBM Reference
- No IBM AIX entry — Xbox 360 VMX128 extension only.
- Xbox 360 XDK, Altivec-128 (VMX128) extensions. A 3-way dot product is a direct mirror of D3D9's
float3 dot. - IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic for the base float arithmetic semantics.