Sylpheed/tools/ppc-manual/memory/lvebx.md

lvebx — Load Vector Element Byte Indexed

Category: Memory · Form: X · Opcode: 0x7c00000e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvebx	lvebx	—	Load Vector Element Byte Indexed

Syntax

lvebx [VD], [RA0], [RB]

Encoding

lvebx — form X

• Opcode word: 0x7c00000e
• Primary opcode (bits 0–5): 31
• Extended opcode: 7
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lvebx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvebx: read	Source GPR.
VD	lvebx: write	Destination vector register.

Register Effects

lvebx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvebx

• Canary XML: tools/ppc-instructions.xml — search for mnem="lvebx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:73
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:136
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:867

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lvebx(PPCHIRBuilder& f, const InstrData& i) {
  // Same as lvx.
  Value* ea =
      f.And(CalculateEA_0(f, i.X.RA, i.X.RB), f.LoadConstantUint64(~0xFull));
  f.StoreVR(i.X.RT, f.ByteSwap(f.Load(ea, VEC128_TYPE)));
  return 0;
}

Special Cases & Edge Conditions

• Single-byte element load. Architecturally lvebx loads exactly one byte from EA and places it in lane EA mod 16 of the destination vector; the other 15 lanes are undefined (PowerISA permits implementations to leave them as garbage). Real hardware: lane EA mod 16 gets the byte, others are unspecified.
• Xenia simplification — full-line read. The xenia snapshot is shared with lvehx / lvewx and reads the entire 16-byte aligned line (ea & ~0xF, then 16 bytes), placing it in VD. This is stronger than the architectural guarantee — every lane is filled with whatever happened to be at the line — but matches the practical idiom of using these single-element loads to assemble a vector. Code that depends on undefined-lane behaviour will still produce well-defined output under xenia.
• Operand order subtle. Unlike lvx, the architectural EA is not masked. The lane is EA & 0xF. Xenia's force-align mask (& !0xF) is a deliberate emulator simplification.
• RA0 semantics. When RA = 0, base is literal zero; lvebx VD, 0, RB reads the byte at RB (and, in xenia, the surrounding aligned line).
• No update form. No lvebux exists. Pointer-bumping requires a separate addi.
• No VMX128 sibling. There is no lvebx128 — the single-byte load family was kept Altivec-only in the Xbox 360 VMX128 extension, since 16-byte aligned loads (lvx128) plus vperm/vsel are usually faster.
• Common idiom. Pair with vperm or vsplt* to broadcast the loaded byte to all lanes, or with vinsertb / shifts to assemble a vector from non-adjacent memory locations.

Related Instructions

• lvehx, lvewx — half-word and word element loads.
• lvx, lvxl — full 16-byte aligned vector loads.
• lvlx, lvrx — load-left / load-right partial-vector ops for unaligned vector I/O.
• stvebx — symmetric single-byte store.

IBM Reference

• AIX 7.3 — lvebx (Load Vector Element Byte Indexed)
• PowerISA v2.07B Book I "Vector Facility" § "Vector Load and Store" for lane-placement rules.