Sylpheed/tools/ppc-manual/memory/stvebx.md

stvebx — Store Vector Element Byte Indexed

Category: Memory · Form: X · Opcode: 0x7c00010e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvebx	stvebx	—	Store Vector Element Byte Indexed

Syntax

stvebx [VS], [RA0], [RB]

Encoding

stvebx — form X

• Opcode word: 0x7c00010e
• Primary opcode (bits 0–5): 31
• Extended opcode: 135
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
VS	stvebx: read	Source vector register (alias for VD on stores).
RA0	stvebx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvebx: read	Source GPR.

Register Effects

stvebx

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvebx

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvebx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:152
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:257
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:893

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvebx(PPCHIRBuilder& f, const InstrData& i) {
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  Value* el = f.And(f.Truncate(ea, INT8_TYPE), f.LoadConstantUint8(0xF));
  Value* v = f.Extract(f.LoadVR(i.X.RT), el, INT8_TYPE);
  f.Store(ea, v);
  return 0;
}

Special Cases & Edge Conditions

• Single-byte element store. Architecturally stvebx writes exactly one byte from lane EA mod 16 of VS to address EA. Other lanes are unaffected, and other memory bytes are unaffected.
• Xenia simplification — full 16-byte write. The xenia snapshot is shared with stvehx / stvewx and writes the entire 16-byte aligned line (ea & ~0xF, then 16 bytes from the vector). This is stronger than the architectural single-byte store — it overwrites 15 adjacent bytes with whatever the source vector holds. Code that depends on architectural per-byte granularity (e.g. interleaved writes from multiple threads / DMA agents into the same line) may behave differently than on hardware.
• RA0 semantics. RA = 0 selects literal zero.
• No update form, no VMX128 sibling. No stvebux; no stvebx128 — single-byte stores were kept Altivec-only in the Xbox 360 extension.
• Big-endian within the line. Lane 0 of VS corresponds to the byte at the aligned base address.
• Common idiom. Pair with vsplt* to broadcast a value, then stvebx to write one byte. Less efficient than stb from a GPR; rare in compiled code.
• Hardware fault model. A protected or unmapped page raises a DSI exception just as for any store.

Related Instructions

• stvehx, stvewx — single half / single word element stores.
• stvx, stvxl — full 16-byte aligned vector stores.
• stvlx, stvrx — store-left / store-right unaligned vector ops.
• lvebx — symmetric single-byte load.

IBM Reference

• AIX 7.3 — stvebx (Store Vector Element Byte Indexed)
• PowerISA v2.07B Book I "Vector Facility" § "Vector Load and Store" for canonical per-byte semantics.