Sylpheed/tools/ppc-manual/memory/lwarx.md

lwarx — Load Word and Reserve Indexed

Category: Memory · Form: X · Opcode: 0x7c000028

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lwarx	lwarx	—	Load Word and Reserve Indexed

Syntax

lwarx [RD], [RA0], [RB]

Encoding

lwarx — form X

• Opcode word: 0x7c000028
• Primary opcode (bits 0–5): 31
• Extended opcode: 20
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lwarx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lwarx: read	Source GPR.
RD	lwarx: write	Destination GPR.

Register Effects

lwarx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lwarx

• Canary XML: tools/ppc-instructions.xml — search for mnem="lwarx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:795
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:158
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:869

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lwarx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // RESERVE <- 1
  // RESERVE_LENGTH <- 4
  // RESERVE_ADDR <- real_addr(EA)
  // RT <- i32.0 || MEM(EA, 4)

  // NOTE: we assume we are within a global lock.
  // We could assert here that the block (or its parent) has taken a global lock
  // already, but I haven't see anything but interrupt callbacks (which are
  // always under a global lock) do that yet.
  // We issue a memory barrier here to make sure that we get good values.

  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  if (cvars::no_reserved_ops) {
    f.StoreGPR(i.X.RT,
               f.ZeroExtend(f.ByteSwap(f.Load(ea, INT32_TYPE)), INT64_TYPE));

  } else {
    f.MemoryBarrier();

    Value* rt =
        f.ZeroExtend(f.ByteSwap(f.LoadWithReserve(ea, INT32_TYPE)), INT64_TYPE);
    f.StoreGPR(i.X.RT, rt);
  }
  return 0;
}

Special Cases & Edge Conditions

• Reservation set on the addressed word. Loads MEM(EA, 4) zero-extended to 64 bits and atomically establishes a reservation on EA. A subsequent stwcx at the same address completes only if the reservation is still valid. Together they form the canonical 32-bit load-linked / store-conditional pair for lock-free updates and futexes.
• One reservation per thread. Xenia's snapshot writes reserved_addr, reserved_val, and has_reservation in the per-context state. Hardware behaves the same: each hardware thread has at most one reservation. A second lwarx (or ldarx) discards the previous reservation.
• Granule. Architecturally one naturally-aligned word; on Xenon the practical reservation granule is one cache line (128 bytes) — any store to that line by another agent invalidates the reservation. Xenia simplifies to per-address tracking, which can let real-hardware-failing pairs succeed under emulation.
• Alignment requirement. EA must be 4-byte aligned. An unaligned lwarx raises an alignment exception on hardware; xenia does not check.
• RA0 semantics. When RA = 0, base is literal zero — lwarx RT, 0, RB reads at exact RB.
• Reservation-loss events. Any exception, context switch, or store by another thread to the reserved line clears the reservation. Application code treats stwcx. failure (CR0[EQ]=0) as a normal retry condition.
• Pair atomically. Code must be lwarx ... do work ... stwcx. with no intervening loads/stores that could reorder. Optionally fence with lwsync inside the loop.

Related Instructions

• stwcx — store-conditional word (the matching half of the pair).
• ldarx / stdcx — 64-bit reservation pair.
• lwz, lwzx — non-reserving word loads.
• sync, lwsync, isync — barriers commonly placed around reservation pairs.

IBM Reference

• AIX 7.3 — lwarx (Load Word and Reserve Indexed)
• PowerISA v2.07B Book II § "Atomic Update Primitives" for the reservation model and granule rules.