Sylpheed/tools/ppc-manual/memory/stdcx.md

stdcx — Store Doubleword Conditional Indexed

Category: Memory · Form: X · Opcode: 0x7c0001ad

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stdcx	stdcx	—	Store Doubleword Conditional Indexed

Syntax

stdcx. [RS], [RA0], [RB]

Encoding

stdcx — form X

• Opcode word: 0x7c0001ad
• Primary opcode (bits 0–5): 31
• Extended opcode: 214
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	stdcx: read	Source GPR (alias for RD in some stores).
RA0	stdcx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stdcx: read	Source GPR.
CR	stdcx: write	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

stdcx

• Reads (always): RS, RA0, RB
• Reads (conditional): none
• Writes (always): CR
• Writes (conditional): none

Status-Register Effects

• stdcx: CR0 ← signed-compare(result, 0) with SO ← XER[SO] (always).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stdcx

• Canary XML: tools/ppc-instructions.xml — search for mnem="stdcx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:827
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:232
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:904

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stdcx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // RESERVE stuff...
  // MEM(EA, 8) <- (RS)
  // n <- 1 if store performed
  // CR0[LT GT EQ SO] = 0b00 || n || XER[SO]

  // NOTE: we assume we are within a global lock.
  // As we have been exclusively executing this entire time, we assume that no
  // one else could have possibly touched the memory and must always succeed.
  // We use atomic compare exchange here to support reserved load/store without
  // being under the global lock (flag disable_global_lock - see mtmsr/mtmsrd).
  // This will always succeed if under the global lock, however.

  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  Value* rt = f.ByteSwap(f.LoadGPR(i.X.RT));

  if (cvars::no_reserved_ops) {
    f.Store(ea, rt);

    f.StoreContext(offsetof(PPCContext, cr0.cr0_eq), f.LoadConstantInt8(1));
  } else {
    Value* v = f.StoreWithReserve(ea, rt, INT64_TYPE);

    f.StoreContext(offsetof(PPCContext, cr0.cr0_eq), v);
  }
  f.StoreContext(offsetof(PPCContext, cr0.cr0_lt), f.LoadZeroInt8());
  f.StoreContext(offsetof(PPCContext, cr0.cr0_gt), f.LoadZeroInt8());

  // Issue memory barrier for when we go out of lock and want others to see our
  // updates.
  if (!cvars::no_reserved_ops) {
    f.MemoryBarrier();
  }
  return 0;
}

Special Cases & Edge Conditions

• Always sets Rc=1 (the trailing dot). The mnemonic is stdcx. — there is no non-Rc variant. CR0 is updated unconditionally to communicate success/failure. EQ=1 means the conditional store succeeded; EQ=0 means it failed (the prior reservation was cleared and no memory was written).
• Reservation check. Xenia's snapshot tests has_reservation && reserved_addr == ea. On match it performs mem.write_u64, sets EQ=1. On mismatch it leaves memory untouched and sets EQ=0. In both cases the reservation is cleared (has_reservation = false), so a retry must be preceded by a fresh ldarx.
• Hardware granule. PowerISA defines reservation by aligned doubleword; Xenon implementations widen this to one 128-byte cache line. A store by another agent anywhere in the line clears the reservation. Xenia's per-address check is more permissive than hardware.
• Alignment requirement. EA must be 8-byte aligned. Unaligned stdcx. raises an alignment exception on real hardware.
• RA0 semantics. When RA = 0, base is literal zero — stdcx. RS, 0, RB writes at exact RB.
• CR0[SO] reflects XER[SO]. Like all CR-updating ops, CR0[SO] is copied from XER[SO] rather than computed from this instruction.
• Spurious failures permitted. Hardware may report failure even when no actual conflict occurred (e.g. on context switch). Application code treats failure as a normal retry condition.
• Pair atomically with ldarx. Don't interleave loads/stores between the pair; an lwsync inside the loop body is common.

Related Instructions

• ldarx — load-and-reserve doubleword (the matching load).
• stwcx / lwarx — 32-bit reservation pair.
• std, stdx — non-conditional doubleword stores.
• sync, lwsync, isync — barriers used around reservation pairs.

IBM Reference

• AIX 7.3 — stdcx. (Store Doubleword Conditional Indexed)
• PowerISA v2.07B Book II § "Atomic Update Primitives" for canonical reservation semantics and granule rules.