7f8a81b8f8
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.
What each source contributed, measured on the 350 pages before this change:
Operation (pseudocode) 251 pages: fixed boilerplate "derives from the xenia-rs
interpreter"; 99 carry real hand-written seeds
C translation 337 pages: the same kind of boilerplate
xenia-rs snapshot 336 pages: the interpreter arm, pasted in — the only
per-instruction semantics on unseeded pages
links xenia-rs opcode/decoder/interpreter + Canary emitter
Now:
* semantics come from **Xenia Canary**, the reference emulator, read through
`git show` at a pinned upstream commit (`origin/canary_experimental`,
f21ebd49e9). Not our checkout: it carries instrumentation and lacked
upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
one-line delegations also the helper that holds the semantics.
* decode references point at `crates/sylpheed-ppc` — the decoder that
produces `sylpheed.db` — as in-repo relative links.
* the boilerplate now says what is true, and the C translation guide maps
Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
that `UpdateCR(n, v)` truncates to 32 bits).
* `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
missing sources are now errors, not empty results.
Verified:
consistency checks 455 XML entries, 350 families, 598 index keys
hand-written tails 386/386 byte-identical after regeneration
xenia-rs in generated 0
pages with a snapshot 349/350 (was 336) — `dcbi` has no Canary emitter at all
in-repo decoder links 910/910 resolve to a line holding the identifier
emitter boundaries brace counter == column-0 `}` rule on 521/521;
preprocessor model unit-tested (#if 0/#else/#elif)
idempotency re-run: 0 pages updated, 0 working-tree changes
Hand-written notes (outside the generated regions) are not rewritten here:
* 110 links into `../../xenia-rs/...` were dead; they now point at the file in
the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
were dropped because the notes predate that commit — 0 of 441 old line
ranges match it — and a precise-looking wrong anchor is worse than none. The
link text, which carries the author's line numbers, is unchanged.
* 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
114 need checking one by one, and some invert — e.g. `divdx` notes a correct
64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
a deliberate pass rather than a blind substitution.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
273 lines
11 KiB
Markdown
273 lines
11 KiB
Markdown
# `std` — Store Doubleword
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> **Category:** [Memory](../categories/memory.md) · **Form:** [DS](../forms/DS.md) · **Opcode:** `0xf8000000`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `std` | `std` | — | Store Doubleword |
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| `stdu` | `stdu` | — | Store Doubleword with Update |
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| `stdux` | `stdux` | — | Store Doubleword with Update Indexed |
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| `stdx` | `stdx` | — | Store Doubleword Indexed |
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## Syntax
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```asm
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std [RS], [ds]([RA0])
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stdu [RS], [ds]([RA])
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stdux [RS], [RA], [RB]
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stdx [RS], [RA0], [RB]
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```
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## Encoding
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### `std` — form `DS`
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- **Opcode word:** `0xf8000000`
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- **Primary opcode (bits 0–5):** `62`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0) |
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| 16–29 | `DS` | 14-bit signed word-scaled displacement |
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| 30–31 | `XO` | extended opcode |
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### `stdu` — form `DS`
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- **Opcode word:** `0xf8000001`
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- **Primary opcode (bits 0–5):** `62`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0) |
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| 16–29 | `DS` | 14-bit signed word-scaled displacement |
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| 30–31 | `XO` | extended opcode |
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### `stdux` — form `X`
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- **Opcode word:** `0x7c00016a`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `181`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `stdx` — form `X`
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- **Opcode word:** `0x7c00012a`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `149`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RS` | std: read; stdu: read; stdux: read; stdx: read | Source GPR (alias for RD in some stores). |
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| `RA` | std: read; stdu: read; stdu: write; stdux: read; stdux: write | Source GPR (`r0`–`r31`). |
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| `ds` | std: read; stdu: read | 14-bit signed word-aligned displacement (`DS << 2`). |
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| `RB` | stdux: read; stdx: read | Source GPR. |
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| `RA0` | stdx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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## Register Effects
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### `std`
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- **Reads (always):** `RS`, `RA`, `ds`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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### `stdu`
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- **Reads (always):** `RS`, `RA`, `ds`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** _none_
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### `stdux`
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- **Reads (always):** `RS`, `RA`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** _none_
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### `stdx`
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- **Reads (always):** `RS`, `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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EA <- (RA|0) + EXTS(ds || 0b00)
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MEM(EA, 8) <- (RS)
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`std`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="std"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:575`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L575)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:230`](../../../crates/sylpheed-ppc/src/opcode.rs#L230)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:514`](../../../crates/sylpheed-ppc/src/decoder.rs#L514)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_std(PPCHIRBuilder& f, const InstrData& i) {
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// if RA = 0 then
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// b <- 0
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// else
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// b <- (RA)
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// EA <- b + EXTS(DS || 0b00)
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// MEM(EA, 8) <- (RS)
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Value* b;
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if (i.DS.RA == 0) {
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b = f.LoadZeroInt64();
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} else {
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b = f.LoadGPR(i.DS.RA);
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}
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Value* offset = f.LoadConstantInt64(XEEXTS16(i.DS.DS << 2));
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f.StoreOffset(b, offset, f.ByteSwap(f.LoadGPR(i.DS.RT)));
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return 0;
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}
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```
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</details>
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**`stdu`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stdu"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:594`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L594)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:233`](../../../crates/sylpheed-ppc/src/opcode.rs#L233)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:515`](../../../crates/sylpheed-ppc/src/decoder.rs#L515)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_stdu(PPCHIRBuilder& f, const InstrData& i) {
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// EA <- (RA) + EXTS(DS || 0b00)
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// MEM(EA, 8) <- (RS)
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// RA <- EA
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Value* ea = CalculateEA_i(f, i.DS.RA, XEEXTS16(i.DS.DS << 2));
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f.Store(ea, f.ByteSwap(f.LoadGPR(i.DS.RT)));
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StoreEA(f, i.DS.RA, ea);
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return 0;
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}
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```
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</details>
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**`stdux`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stdux"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:604`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L604)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:234`](../../../crates/sylpheed-ppc/src/opcode.rs#L234)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:901`](../../../crates/sylpheed-ppc/src/decoder.rs#L901)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_stdux(PPCHIRBuilder& f, const InstrData& i) {
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// EA <- (RA) + (RB)
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// MEM(EA, 8) <- (RS)
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// RA <- EA
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Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
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f.Store(ea, f.ByteSwap(f.LoadGPR(i.X.RT)));
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StoreEA(f, i.X.RA, ea);
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return 0;
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}
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```
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</details>
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**`stdx`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stdx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:614`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L614)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:235`](../../../crates/sylpheed-ppc/src/opcode.rs#L235)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:896`](../../../crates/sylpheed-ppc/src/decoder.rs#L896)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_stdx(PPCHIRBuilder& f, const InstrData& i) {
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// if RA = 0 then
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// b <- 0
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// else
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// b <- (RA)
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// EA <- b + (RB)
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// MEM(EA, 8) <- (RS)
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Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
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f.Store(ea, f.ByteSwap(f.LoadGPR(i.X.RT)));
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **DS-form, not D-form.** Like [`ld`](ld.md), `std` uses a 14-bit signed displacement scaled by 4 (`EXTS(ds || 0b00)`). Bits 30–31 are the extended opcode used to distinguish `std` (XO=0) from `stdu` (XO=1). Assemblers verify the byte displacement is a multiple of 4.
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- **Big-endian write.** The 64-bit value of `RS` is written most-significant-byte-first: `RS[0:7]` to `EA`, `RS[56:63]` to `EA+7`. Xenia's `mem.write_u64` performs the host-side byte swap if needed.
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- **`RA0` for `std` and `stdx`.** When `RA = 0`, base is the literal zero. Update forms `stdu` / `stdux` invoke `RA = 0` as an invalid form (no `RA = RS` collision possible — `RS` and `RA` are independent encoding fields, and even if equal the store reads `RS` first).
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- **Update-form post-write.** `stdu` / `stdux` write `EA` to `RA` after the store. Order is store-then-update.
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- **Alignment.** Xenon tolerates unaligned doubleword stores. PowerISA permits implementations to raise alignment exceptions; portable code keeps doublewords 8-byte aligned. Cache-inhibited storage may force alignment.
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- **Cache-line behaviour.** A doubleword store fits inside one Xenon cache line (128 B), so it's a single line write. A doubleword store that **straddles** a line boundary triggers two line accesses — keep doublewords 8-byte aligned to avoid the cost.
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- **64-bit pointer / counter stores.** Xbox 360 user code is 32-bit, but kernel structures, TOC entries, and 64-bit counters are stored with `std`.
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## Related Instructions
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- [`stw`](stw.md), [`sth`](sth.md), [`stb`](stb.md) — narrower integer stores.
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- [`stdbrx`](stdbrx.md) — byte-reversed doubleword store.
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- [`stdcx`](stdcx.md) — store-conditional (the doubleword reservation pair end).
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- [`ld`](ld.md), [`ldu`](ld.md), [`ldx`](ld.md), [`ldux`](ld.md) — corresponding loads.
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- [`stfd`](stfd.md) — FP doubleword store (same width, different register file).
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## IBM Reference
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- [AIX 7.3 — `std` (Store Doubleword)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-std-store-doubleword-instruction)
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- [AIX 7.3 — `stdu` / `stdx` / `stdux`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stdu-store-doubleword-update-instruction)
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