7f8a81b8f8
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.
What each source contributed, measured on the 350 pages before this change:
Operation (pseudocode) 251 pages: fixed boilerplate "derives from the xenia-rs
interpreter"; 99 carry real hand-written seeds
C translation 337 pages: the same kind of boilerplate
xenia-rs snapshot 336 pages: the interpreter arm, pasted in — the only
per-instruction semantics on unseeded pages
links xenia-rs opcode/decoder/interpreter + Canary emitter
Now:
* semantics come from **Xenia Canary**, the reference emulator, read through
`git show` at a pinned upstream commit (`origin/canary_experimental`,
f21ebd49e9). Not our checkout: it carries instrumentation and lacked
upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
one-line delegations also the helper that holds the semantics.
* decode references point at `crates/sylpheed-ppc` — the decoder that
produces `sylpheed.db` — as in-repo relative links.
* the boilerplate now says what is true, and the C translation guide maps
Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
that `UpdateCR(n, v)` truncates to 32 bits).
* `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
missing sources are now errors, not empty results.
Verified:
consistency checks 455 XML entries, 350 families, 598 index keys
hand-written tails 386/386 byte-identical after regeneration
xenia-rs in generated 0
pages with a snapshot 349/350 (was 336) — `dcbi` has no Canary emitter at all
in-repo decoder links 910/910 resolve to a line holding the identifier
emitter boundaries brace counter == column-0 `}` rule on 521/521;
preprocessor model unit-tested (#if 0/#else/#elif)
idempotency re-run: 0 pages updated, 0 working-tree changes
Hand-written notes (outside the generated regions) are not rewritten here:
* 110 links into `../../xenia-rs/...` were dead; they now point at the file in
the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
were dropped because the notes predate that commit — 0 of 441 old line
ranges match it — and a precise-looking wrong anchor is worse than none. The
link text, which carries the author's line numbers, is unchanged.
* 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
114 need checking one by one, and some invert — e.g. `divdx` notes a correct
64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
a deliberate pass rather than a blind substitution.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
263 lines
10 KiB
Markdown
263 lines
10 KiB
Markdown
# `stfd` — Store Floating-Point Double
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> **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0xd8000000`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `stfd` | `stfd` | — | Store Floating-Point Double |
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| `stfdu` | `stfdu` | — | Store Floating-Point Double with Update |
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| `stfdux` | `stfdux` | — | Store Floating-Point Double with Update Indexed |
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| `stfdx` | `stfdx` | — | Store Floating-Point Double Indexed |
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## Syntax
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```asm
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stfd [FS], [d]([RA0])
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stfdu [FS], [d]([RA])
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stfdux [FS], [RA], [RB]
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stfdx [FS], [RA0], [RB]
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```
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## Encoding
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### `stfd` — form `D`
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- **Opcode word:** `0xd8000000`
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- **Primary opcode (bits 0–5):** `54`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS when storing) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
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| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
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### `stfdu` — form `D`
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- **Opcode word:** `0xdc000000`
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- **Primary opcode (bits 0–5):** `55`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS when storing) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
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| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
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### `stfdux` — form `X`
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- **Opcode word:** `0x7c0005ee`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `759`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `stfdx` — form `X`
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- **Opcode word:** `0x7c0005ae`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `727`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `FS` | stfd: read; stfdu: read; stfdux: read; stfdx: read | Source floating-point register. |
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| `RA0` | stfd: read; stfdx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `d` | stfd: read; stfdu: read | 16-bit signed displacement (`d`) added to the base address register. |
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| `RA` | stfdu: read; stfdu: write; stfdux: read; stfdux: write | Source GPR (`r0`–`r31`). |
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| `RB` | stfdux: read; stfdx: read | Source GPR. |
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## Register Effects
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### `stfd`
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- **Reads (always):** `FS`, `RA0`, `d`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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### `stfdu`
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- **Reads (always):** `FS`, `RA`, `d`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** _none_
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### `stfdux`
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- **Reads (always):** `FS`, `RA`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** _none_
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### `stfdx`
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- **Reads (always):** `FS`, `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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EA <- (RA|0) + EXTS(d)
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MEM(EA, 8) <- (FRS)
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`stfd`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfd"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1014`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1014)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:237`](../../../crates/sylpheed-ppc/src/opcode.rs#L237)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:492`](../../../crates/sylpheed-ppc/src/decoder.rs#L492)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_stfd(PPCHIRBuilder& f, const InstrData& i) {
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// if RA = 0 then
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// b <- 0
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// else
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// b <- (RA)
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// EA <- b + EXTS(D)
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// MEM(EA, 8) <- (FRS)
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Value* ea = CalculateEA_0_i(f, i.D.RA, XEEXTS16(i.D.DS));
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f.Store(ea, f.ByteSwap(f.Cast(f.LoadFPR(i.D.RT), INT64_TYPE)));
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return 0;
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}
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```
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</details>
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**`stfdu`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfdu"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1026`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1026)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:238`](../../../crates/sylpheed-ppc/src/opcode.rs#L238)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:493`](../../../crates/sylpheed-ppc/src/decoder.rs#L493)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_stfdu(PPCHIRBuilder& f, const InstrData& i) {
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// EA <- (RA) + EXTS(D)
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// MEM(EA, 8) <- (FRS)
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// RA <- EA
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Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS));
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f.Store(ea, f.ByteSwap(f.Cast(f.LoadFPR(i.D.RT), INT64_TYPE)));
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StoreEA(f, i.D.RA, ea);
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return 0;
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}
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```
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</details>
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**`stfdux`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfdux"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1036`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1036)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:239`](../../../crates/sylpheed-ppc/src/opcode.rs#L239)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:952`](../../../crates/sylpheed-ppc/src/decoder.rs#L952)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_stfdux(PPCHIRBuilder& f, const InstrData& i) {
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// EA <- (RA) + (RB)
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// MEM(EA, 8) <- (FRS)
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// RA <- EA
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Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
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f.Store(ea, f.ByteSwap(f.Cast(f.LoadFPR(i.X.RT), INT64_TYPE)));
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StoreEA(f, i.X.RA, ea);
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return 0;
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}
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```
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</details>
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**`stfdx`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfdx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1046`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1046)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:240`](../../../crates/sylpheed-ppc/src/opcode.rs#L240)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:951`](../../../crates/sylpheed-ppc/src/decoder.rs#L951)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_stfdx(PPCHIRBuilder& f, const InstrData& i) {
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// if RA = 0 then
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// b <- 0
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// else
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// b <- (RA)
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// EA <- b + (RB)
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// MEM(EA, 8) <- (FRS)
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Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
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f.Store(ea, f.ByteSwap(f.Cast(f.LoadFPR(i.X.RT), INT64_TYPE)));
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Bit-exact double store.** Writes the 64-bit IEEE binary64 contents of `FRS` directly to memory; no rounding, no format conversion. The xenia snapshot calls `mem.write_f64(ea, ctx.fpr[instr.rs()])`, which preserves the exact bit pattern (including signalling NaNs).
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- **No FPSCR side effects.** Like [`lfd`](lfd.md), `stfd` cannot raise IEEE exceptions: there is no rounding step. Contrast [`stfs`](stfs.md), where double→single rounding **can** raise inexact / overflow / underflow.
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- **`RA0` (non-update forms).** `RA = 0` in `stfd` and `stfdx` selects literal zero. Update forms `stfdu` / `stfdux` invoke `RA = 0` as an invalid form.
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- **Update-form post-write.** `stfdu` / `stfdux` write the computed `EA` back to `RA` after the store. No `FRS` / `RA` collision possible — `RS` is an FPR, `RA` is a GPR.
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- **Big-endian write.** Byte at `EA` is the FPR's most-significant byte (sign + part of exponent), byte at `EA+7` is the least-significant mantissa byte. Xenia's `mem.write_f64` performs host-side byte-swap.
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- **Alignment.** Xenon tolerates unaligned 8-byte FP stores. PowerISA permits implementations to raise alignment exceptions on cache-inhibited storage.
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- **MSR[FP] required.** Disabled FP unit raises Floating-Point Unavailable.
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## Related Instructions
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- [`lfd`](lfd.md), [`lfdu`](lfd.md), [`lfdx`](lfd.md), [`lfdux`](lfd.md) — corresponding loads.
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- [`stfs`](stfs.md) — single-precision store with format conversion (can raise FPSCR).
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- [`stfiwx`](stfiwx.md) — store low 32 bits of FPR as integer word.
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- [`std`](std.md) — integer doubleword store (same width, GPR source).
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## IBM Reference
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- [AIX 7.3 — `stfd` (Store Floating-Point Double)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stfd-store-floating-point-double-instruction)
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- [AIX 7.3 — `stfdu` / `stfdx` / `stfdux`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stfdu-store-floating-point-double-update-instruction)
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