10dc260f0c
CONSOLIDATION.md Phase 6. Both lived untracked in the project root -- on one
disk, backed up by nothing.
tools/ppc-manual/ 393 files, 3.7 MB. 455 instructions, 350 family pages,
598 mnemonics resolvable through index.json, plus the
generator that produced them.
tools/run-canary.sh the oracle launcher.
🔴 THE LAUNCHER WAS BROKEN IN TWO WAYS AND IS REWRITTEN, not copied:
* it pointed at `xenia-rs/sylpheed.iso`, a SYMLINK. Wine cannot resolve one
and says "path invalid", which reads as a corrupt image rather than a path
problem -- it has cost a session before. It now points at the real file and
warns if handed a symlink.
* it hardcoded one machine's absolute paths, and named `xenia-rs`, which this
consolidation retires. Now derived from the script's own location, with
SYLPH_CANARY_BIN / SYLPH_ISO overrides and a check that each exists.
The standing constraints are in its header where someone will read them: one
emulator at a time, Canary runs MUTED, and never judge a crash or a hang from
a Bash-launched run -- a SIGKILL that looked like the binary was the editor's
process supervisor.
⚠️ The manual's GENERATOR reads the xenia-rs source tree, which is going away.
Its decoder now lives here as crates/sylpheed-ppc, so the generator must be
repointed before it is run again. Recorded in the README rather than left for
someone to discover; the manual's content is checked in and regenerates from
nothing implicitly.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
131 lines
5.3 KiB
Markdown
131 lines
5.3 KiB
Markdown
# `stdbrx` — Store Doubleword Byte-Reverse Indexed
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> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c000528`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `stdbrx` | `stdbrx` | — | Store Doubleword Byte-Reverse Indexed |
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## Syntax
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```asm
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stdbrx [RS], [RA0], [RB]
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```
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## Encoding
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### `stdbrx` — form `X`
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- **Opcode word:** `0x7c000528`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `660`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RS` | stdbrx: read | Source GPR (alias for RD in some stores). |
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| `RA0` | stdbrx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `RB` | stdbrx: read | Source GPR. |
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## Register Effects
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### `stdbrx`
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- **Reads (always):** `RS`, `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`stdbrx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stdbrx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:691`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L691)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:69`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L69)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:829`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L829)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4632-4639`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4632-L4639)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::stdbrx => {
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let ea = ea_indexed(ctx, instr);
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if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
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if t.has_active_reservers() { t.invalidate_for_write(ea); }
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}
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mem.write_u64(ea, ctx.gpr[instr.rs()].swap_bytes());
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Writes little-endian doubleword.** Reverses the 8 bytes of `RS` and stores them at `EA`. Compared to a regular `std`, the byte at `EA` becomes `RS[56:63]` (least-significant), and the byte at `EA+7` becomes `RS[0:7]` (most-significant). The xenia snapshot calls `mem.write_u64(ea, ctx.gpr[instr.rs()].swap_bytes())`.
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- **Used to emit little-endian payloads.** Symmetric counterpart of [`ldbrx`](ldbrx.md). Common when writing PC-side file formats, network packets, or PE/COFF headers from PowerPC code.
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- **X-form only — no update form, no DS-form.** Only the indexed form exists. `EA = (RA|0) + RB`. Pointer-bumping requires a separate `addi`.
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- **`RA0` semantics.** When `RA = 0`, base is literal zero. `stdbrx RS, 0, RB` writes at exact `RB`.
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- **Alignment.** Hardware tolerates unaligned 8-byte writes. Cache-inhibited storage may raise alignment exceptions on real hardware.
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- **No CR / FPSCR effects.** Pure data movement.
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- **Cache-line straddling cost.** As with `std`, writes that cross a 128-byte line boundary touch two cache lines; keep doublewords 8-byte aligned for best performance.
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## Related Instructions
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- [`ldbrx`](ldbrx.md) — load doubleword byte-reverse (the matching load).
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- [`stwbrx`](stwbrx.md), [`sthbrx`](sthbrx.md) — narrower byte-reverse stores.
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- [`std`](std.md), [`stdx`](std.md) — non-reversing doubleword stores.
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## IBM Reference
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- [AIX 7.3 — `stdbrx` (Store Doubleword Byte-Reverse Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stdbrx-store-double-word-byte-reverse-indexed-instruction)
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- `PowerISA v2.07B Book II` § "Byte-Reverse Storage Access".
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