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dedcf37867ce3a51f00e90aef2ac2948e3eab76b
Sylpheed/tools/ppc-manual/alu/andix.md
sim dedcf37867 docs(ppc-manual): quote Canary and our own decoder, not the retired xenia-rs 
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.

What each source contributed, measured on the 350 pages before this change:

  Operation (pseudocode)  251 pages: fixed boilerplate "derives from the xenia-rs
                          interpreter"; 99 carry real hand-written seeds
  C translation           337 pages: the same kind of boilerplate
  xenia-rs snapshot       336 pages: the interpreter arm, pasted in — the only
                          per-instruction semantics on unseeded pages
  links                   xenia-rs opcode/decoder/interpreter + Canary emitter

Now:

  * semantics come from **Xenia Canary**, the reference emulator, read through
    `git show` at a pinned upstream commit (`origin/canary_experimental`,
    f21ebd49e9). Not our checkout: it carries instrumentation and lacked
    upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
    Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
    one-line delegations also the helper that holds the semantics.
  * decode references point at `crates/sylpheed-ppc` — the decoder that
    produces `sylpheed.db` — as in-repo relative links.
  * the boilerplate now says what is true, and the C translation guide maps
    Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
    that `UpdateCR(n, v)` truncates to 32 bits).
  * `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
    missing sources are now errors, not empty results.

Verified:

  consistency checks        455 XML entries, 350 families, 598 index keys
  hand-written tails        386/386 byte-identical after regeneration
  xenia-rs in generated     0
  pages with a snapshot     349/350 (was 336) — `dcbi` has no Canary emitter at all
  in-repo decoder links     910/910 resolve to a line holding the identifier
  emitter boundaries        brace counter == column-0 `}` rule on 521/521;
                            preprocessor model unit-tested (#if 0/#else/#elif)
  idempotency               re-run: 0 pages updated, 0 working-tree changes

Hand-written notes (outside the generated regions) are not rewritten here:

  * 110 links into `../../xenia-rs/...` were dead; they now point at the file in
    the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
    were dropped because the notes predate that commit — 0 of 441 old line
    ranges match it — and a precise-looking wrong anchor is worse than none. The
    link text, which carries the author's line numbers, is unchanged.
  * 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
    for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
    114 need checking one by one, and some invert — e.g. `divdx` notes a correct
    64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
    a deliberate pass rather than a blind substitution.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 20:34:34 +02:00

5.5 KiB
Raw Blame History

andi. — AND Immediate

Category: Integer ALU · Form: D · Opcode: 0x70000000

Assembler Mnemonics

Mnemonic XML entry Flags Description
andi. andi. — AND Immediate

Syntax

andi. [RA], [RS], [UIMM]

Encoding

andi. — form D

  • Opcode word: 0x70000000
  • Primary opcode (bits 0–5): 28
  • Extended opcode: —
  • Synchronising: no
Bits Field Meaning
0–5 OPCD primary opcode
6–10 RT destination GPR (or RS when storing)
11–15 RA source GPR (0 ⇒ literal 0 for RA0 forms)
16–31 D/SI/UI 16-bit signed or unsigned immediate

Operands

Field Role Description
RS andi.: read Source GPR (alias for RD in some stores).
UIMM andi.: read 16-bit unsigned immediate. Zero-extended.
RA andi.: write Source GPR (r0–r31).
CR andi.: write Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

andi.

  • Reads (always): RS, UIMM
  • Reads (conditional): none
  • Writes (always): RA, CR
  • Writes (conditional): none

Status-Register Effects

  • andi.: CR0 ← signed-compare(result, 0) with SO ← XER[SO] (always).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

andi.

Canary emitter (frozen snapshot @ f21ebd49e9) 
int InstrEmit_andix(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- (RS) & (i48.0 || UI)
  Value* ra = f.And(f.LoadGPR(i.D.RT), f.LoadConstantUint64(XEEXTZ16(i.D.DS)));
  f.StoreGPR(i.D.RA, ra);
  f.UpdateCR(0, ra);
  return 0;
}

Special Cases & Edge Conditions

  • Always Rc=1. There is no andi (without the dot). The mnemonic is andi. and the encoding always updates CR0. If you need a non-record AND-with-immediate, you have to materialise the immediate first (e.g. with li/lis) and use andx.
  • Immediate is zero-extended. The 16-bit UIMM is widened with zeros, so andi. rA, rS, 0xFFFF masks rS to its low 16 bits — the high 48 bits of the 64-bit register are forced to zero.
  • Cannot mask the high half of a register in one instruction. The immediate covers bits 48–63 only; for higher bits use andisx (covers bits 32–47) or compose with rlwinm/rldicl.
  • CR0 update is unconditional. This is part of the encoding, not a flag — the primary opcode (28) is andi..
  • Common idiom: andi. r0, rN, mask to test bits without disturbing the source — but note r0 is overwritten and CR0 is set. If you only need the CR result, prefer extrwi/rlwinm. for arbitrary masks.
  • 64-bit CR update on Xenon, 32-bit in xenia-rs. Since the AND result has zeros in bits 0–47, the low-32 truncation in interpreter.rs:321 is harmless here — the result fits in 16 bits, so spec and xenia agree.

Related Instructions

  • andisx — same op with immediate shifted left 16 (covers bits 32–47).
  • andx, andcx — register AND family.
  • ori, oris, xori, xoris — sister immediate logicals (notably without a record form).
  • rlwinmx — for masks that don't fit into a 16-bit immediate.

IBM Reference

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