Sylpheed/tools/ppc-manual/alu/orx.md

orx — OR

Category: Integer ALU · Form: X · Opcode: 0x7c000378

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
or	orx	—	OR
or.	orx	Rc=1	OR

Syntax

or[Rc] [RA], [RS], [RB]

Encoding

orx — form X

• Opcode word: 0x7c000378
• Primary opcode (bits 0–5): 31
• Extended opcode: 444
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	orx: read	Source GPR (alias for RD in some stores).
RB	orx: read	Source GPR.
RA	orx: write	Source GPR (r0–r31).
CR	orx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

orx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• orx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- (RS) | (RB)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

orx

• Canary XML: tools/ppc-instructions.xml — search for mnem="orx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:773
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:202
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:924

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_orx(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- (RS) | (RB)
  if (i.X.RT == i.X.RB && i.X.RT == i.X.RA && !i.X.Rc) {
    // chrispy: this special version of orx is db16cyc and is heavily used in
    // spinlocks. since we do not emit any code for this we end up wasting a ton
    // of power
    if (i.code == 0x7FFFFB78) {
      f.DelayExecution();
    } else {
      // Sometimes used as no-op.
      f.Nop();
    }
    return 0;
  }
  Value* ra;
  if (i.X.RT == i.X.RB) {
    ra = f.LoadGPR(i.X.RT);
  } else {
    ra = f.Or(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB));
  }
  f.StoreGPR(i.X.RA, ra);
  if (i.X.Rc) {
    f.UpdateCR(0, ra);
  }
  return 0;
}

Special Cases & Edge Conditions

• Canonical "register move". or RA, RS, RS copies RS to RA — assemblers expose this as the simplified mnemonic mr RA, RS (move register). It is the single most common instruction in PPC disassembly after loads/stores.
• Operand convention is X-form (RA destination, RS/RB sources).
• 64-bit operation on Xenon; full bitwise OR across 64 bits.
• No OE or XER side effects. Only Rc=1 updates CR0.
• 64-bit CR update on Xenon, 32-bit in xenia-rs. interpreter.rs:357 truncates with as i32 as i64. For or. RA, RS, RS (i.e. mr.), this means CR0 reflects the low 32 bits of RS only — distinguishable from spec only when the high 32 bits are non-zero with all-zero low 32.
• or 26, 26, 26 is the Xbox 360 NOP variant historically used to mark cache lines or signal the dispatch unit (alongside nop ≡ ori 0,0,0). Disassembly may show this — it has no architectural effect.

Related Instructions

• orcx — OR with complement.
• norx — NOR (and the basis for not).
• andx, xorx, eqvx — sister logicals.
• ori, oris — D-form immediate variants (no record form).
• mr (simplified) — or RA, RS, RS.

IBM Reference

• AIX 7.3 — or (OR)
• AIX 7.3 — mr (Move Register, simplified)