Files
Sylpheed/tools/ppc-manual/alu/subficx.md
sim dedcf37867 docs(ppc-manual): quote Canary and our own decoder, not the retired xenia-rs
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.

What each source contributed, measured on the 350 pages before this change:

  Operation (pseudocode)  251 pages: fixed boilerplate "derives from the xenia-rs
                          interpreter"; 99 carry real hand-written seeds
  C translation           337 pages: the same kind of boilerplate
  xenia-rs snapshot       336 pages: the interpreter arm, pasted in — the only
                          per-instruction semantics on unseeded pages
  links                   xenia-rs opcode/decoder/interpreter + Canary emitter

Now:

  * semantics come from **Xenia Canary**, the reference emulator, read through
    `git show` at a pinned upstream commit (`origin/canary_experimental`,
    f21ebd49e9). Not our checkout: it carries instrumentation and lacked
    upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
    Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
    one-line delegations also the helper that holds the semantics.
  * decode references point at `crates/sylpheed-ppc` — the decoder that
    produces `sylpheed.db` — as in-repo relative links.
  * the boilerplate now says what is true, and the C translation guide maps
    Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
    that `UpdateCR(n, v)` truncates to 32 bits).
  * `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
    missing sources are now errors, not empty results.

Verified:

  consistency checks        455 XML entries, 350 families, 598 index keys
  hand-written tails        386/386 byte-identical after regeneration
  xenia-rs in generated     0
  pages with a snapshot     349/350 (was 336) — `dcbi` has no Canary emitter at all
  in-repo decoder links     910/910 resolve to a line holding the identifier
  emitter boundaries        brace counter == column-0 `}` rule on 521/521;
                            preprocessor model unit-tested (#if 0/#else/#elif)
  idempotency               re-run: 0 pages updated, 0 working-tree changes

Hand-written notes (outside the generated regions) are not rewritten here:

  * 110 links into `../../xenia-rs/...` were dead; they now point at the file in
    the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
    were dropped because the notes predate that commit — 0 of 441 old line
    ranges match it — and a precise-looking wrong anchor is worse than none. The
    link text, which carries the author's line numbers, is unchanged.
  * 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
    for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
    114 need checking one by one, and some invert — e.g. `divdx` notes a correct
    64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
    a deliberate pass rather than a blind substitution.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 20:34:34 +02:00

5.5 KiB
Raw Blame History

subficx — Subtract From Immediate Carrying

Category: Integer ALU · Form: D · Opcode: 0x20000000

Assembler Mnemonics

Mnemonic XML entry Flags Description
subfic subficx Subtract From Immediate Carrying

Syntax

subfic [RD], [RA], [SIMM]

Encoding

subficx — form D

  • Opcode word: 0x20000000
  • Primary opcode (bits 05): 8
  • Extended opcode:
  • Synchronising: no
Bits Field Meaning
05 OPCD primary opcode
610 RT destination GPR (or RS when storing)
1115 RA source GPR (0 ⇒ literal 0 for RA0 forms)
1631 D/SI/UI 16-bit signed or unsigned immediate

Operands

Field Role Description
RA subficx: read Source GPR (r0r31).
SIMM subficx: read 16-bit signed immediate. Sign-extended to 64 bits before use.
RD subficx: write Destination GPR.
CA subficx: write XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.

Register Effects

subficx

  • Reads (always): RA, SIMM
  • Reads (conditional): none
  • Writes (always): RD, CA
  • Writes (conditional): none

Status-Register Effects

  • subficx: XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

subficx

Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_subficx(PPCHIRBuilder& f, const InstrData& i) {
  // RT <- ¬(RA) + EXTS(SI) + 1
  Value* ra = f.LoadGPR(i.D.RA);
  Value* v = f.Sub(f.LoadConstantInt64(XEEXTS16(i.D.DS)), ra);
  f.StoreGPR(i.D.RT, v);
  f.StoreCA(SubDidCarry(f, f.LoadConstantInt64(XEEXTS16(i.D.DS)), ra));
  return 0;
}

Special Cases & Edge Conditions

  • RT ← SIMM RA with XER[CA] always set. Note the operand order: the immediate is the minuend, not the subtrahend. subfic rD, rA, 1 computes 1 - rA, useful for negation-plus-one or one's-complement-style operations.
  • Immediate is sign-extended to 64 bits before the subtract. So subfic rD, rA, -1 computes -1 - rA, equivalent to ~rA.
  • XER[CA] = 1 when SIMM >= RA (no borrow). Computed in xenia as if imm >= ra (interpreter.rs:73) — comparing the sign-extended unsigned representations.
  • No Rc, no OE. This D-form has no flag bits beyond the implicit CA write.
  • No record-form variant. There is no subfic. in the ISA; if you need CR0 to also reflect the result, follow with a cmpwi.
  • Synthesised "subtract immediate". Assemblers sometimes accept subi rD, rA, value as a shorthand for addi rD, rA, -value, but for the carry-producing variant you must use subfic explicitly.
  • Common idiom: subfic rD, rA, 0 computes -rA and sets CA according to whether rA == 0 (no borrow) or rA != 0 (borrow). Equivalent to negx when CA doesn't matter.
  • subfcx — XO-form register version.
  • subfx — register subtract without XER[CA].
  • addic, addicx — dual: add immediate carrying.
  • negx — equivalent to subfic rD, rA, 0 when CA is unwanted.

IBM Reference