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Sylpheed/tools/ppc-manual/alu/sync.md
sim dedcf37867 docs(ppc-manual): quote Canary and our own decoder, not the retired xenia-rs 
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.

What each source contributed, measured on the 350 pages before this change:

  Operation (pseudocode)  251 pages: fixed boilerplate "derives from the xenia-rs
                          interpreter"; 99 carry real hand-written seeds
  C translation           337 pages: the same kind of boilerplate
  xenia-rs snapshot       336 pages: the interpreter arm, pasted in — the only
                          per-instruction semantics on unseeded pages
  links                   xenia-rs opcode/decoder/interpreter + Canary emitter

Now:

  * semantics come from **Xenia Canary**, the reference emulator, read through
    `git show` at a pinned upstream commit (`origin/canary_experimental`,
    f21ebd49e9). Not our checkout: it carries instrumentation and lacked
    upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
    Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
    one-line delegations also the helper that holds the semantics.
  * decode references point at `crates/sylpheed-ppc` — the decoder that
    produces `sylpheed.db` — as in-repo relative links.
  * the boilerplate now says what is true, and the C translation guide maps
    Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
    that `UpdateCR(n, v)` truncates to 32 bits).
  * `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
    missing sources are now errors, not empty results.

Verified:

  consistency checks        455 XML entries, 350 families, 598 index keys
  hand-written tails        386/386 byte-identical after regeneration
  xenia-rs in generated     0
  pages with a snapshot     349/350 (was 336) — `dcbi` has no Canary emitter at all
  in-repo decoder links     910/910 resolve to a line holding the identifier
  emitter boundaries        brace counter == column-0 `}` rule on 521/521;
                            preprocessor model unit-tested (#if 0/#else/#elif)
  idempotency               re-run: 0 pages updated, 0 working-tree changes

Hand-written notes (outside the generated regions) are not rewritten here:

  * 110 links into `../../xenia-rs/...` were dead; they now point at the file in
    the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
    were dropped because the notes predate that commit — 0 of 441 old line
    ranges match it — and a precise-looking wrong anchor is worse than none. The
    link text, which carries the author's line numbers, is unchanged.
  * 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
    for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
    114 need checking one by one, and some invert — e.g. `divdx` notes a correct
    64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
    a deliberate pass rather than a blind substitution.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 20:34:34 +02:00

4.7 KiB
Raw Blame History

sync — Synchronize

Category: Integer ALU · Form: X · Opcode: 0x7c0004ac

Assembler Mnemonics

Mnemonic XML entry Flags Description
sync sync — Synchronize

Syntax

sync

Encoding

sync — form X

  • Opcode word: 0x7c0004ac
  • Primary opcode (bits 0–5): 31
  • Extended opcode: 598
  • Synchronising: no
Bits Field Meaning
0–5 OPCD primary opcode
6–10 RT/FRT/VRT destination
11–15 RA/FRA/VRA source A
16–20 RB/FRB/VRB source B
21–30 XO extended opcode (10 bits)
31 Rc record-form flag

Operands

Field Role Description

Register Effects

sync

  • Reads (always): none
  • Reads (conditional): none
  • Writes (always): none
  • Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

multi-thread memory barrier (heavy). L=0 full sync; L=1 lightweight sync.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

sync

Canary emitter (frozen snapshot @ f21ebd49e9) 
int InstrEmit_sync(PPCHIRBuilder& f, const InstrData& i) {
  f.MemoryBarrier();
  return 0;
}

Special Cases & Edge Conditions

  • Heavy multi-thread memory barrier. All memory accesses (loads and stores, cacheable and not) issued by this thread before sync complete with respect to all other threads/processors before any subsequent memory access begins. Drains the store queue.
  • L field selects sync class. L=0 is full hwsync (the default). L=1 is lwsync — orders only loads-after-loads, loads-after-stores, and stores-after-stores (not stores-after-loads). The Xenon implements both via the same encoding with L (bit 9) selecting variant. Most disassembly shows the unsuffixed sync mnemonic, which assembles to L=0.
  • No register or CR effects. Pure ordering primitive.
  • Used to implement release semantics. A typical lock-release sequence is sync; stw r0, lock. Acquire side uses lwsync after the load.
  • Xenia-rs is a no-op. interpreter.rs:1267 collapses sync, eieio, isync into PC-advance. Since xenia is single-threaded interpretation, host program order subsumes all PPC ordering.
  • Distinct from isync, which orders the instruction stream — sync does not refetch instructions.
  • Slow on real hardware. Hundreds of cycles when the store queue is full; hot paths avoid sync and use lwsync or no barrier when only single-thread ordering is needed.

Related Instructions

  • isync — instruction-fetch barrier.
  • eieio — lighter I/O barrier for caching-inhibited storage.
  • lwsync — same encoding, L=1; not separately enumerated in this page set.

IBM Reference

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