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dedcf37867ce3a51f00e90aef2ac2948e3eab76b
Sylpheed/tools/ppc-manual/control/mtfsb0x.md
sim dedcf37867 docs(ppc-manual): quote Canary and our own decoder, not the retired xenia-rs 
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.

What each source contributed, measured on the 350 pages before this change:

  Operation (pseudocode)  251 pages: fixed boilerplate "derives from the xenia-rs
                          interpreter"; 99 carry real hand-written seeds
  C translation           337 pages: the same kind of boilerplate
  xenia-rs snapshot       336 pages: the interpreter arm, pasted in — the only
                          per-instruction semantics on unseeded pages
  links                   xenia-rs opcode/decoder/interpreter + Canary emitter

Now:

  * semantics come from **Xenia Canary**, the reference emulator, read through
    `git show` at a pinned upstream commit (`origin/canary_experimental`,
    f21ebd49e9). Not our checkout: it carries instrumentation and lacked
    upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
    Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
    one-line delegations also the helper that holds the semantics.
  * decode references point at `crates/sylpheed-ppc` — the decoder that
    produces `sylpheed.db` — as in-repo relative links.
  * the boilerplate now says what is true, and the C translation guide maps
    Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
    that `UpdateCR(n, v)` truncates to 32 bits).
  * `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
    missing sources are now errors, not empty results.

Verified:

  consistency checks        455 XML entries, 350 families, 598 index keys
  hand-written tails        386/386 byte-identical after regeneration
  xenia-rs in generated     0
  pages with a snapshot     349/350 (was 336) — `dcbi` has no Canary emitter at all
  in-repo decoder links     910/910 resolve to a line holding the identifier
  emitter boundaries        brace counter == column-0 `}` rule on 521/521;
                            preprocessor model unit-tested (#if 0/#else/#elif)
  idempotency               re-run: 0 pages updated, 0 working-tree changes

Hand-written notes (outside the generated regions) are not rewritten here:

  * 110 links into `../../xenia-rs/...` were dead; they now point at the file in
    the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
    were dropped because the notes predate that commit — 0 of 441 old line
    ranges match it — and a precise-looking wrong anchor is worse than none. The
    link text, which carries the author's line numbers, is unchanged.
  * 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
    for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
    114 need checking one by one, and some invert — e.g. `divdx` notes a correct
    64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
    a deliberate pass rather than a blind substitution.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 20:34:34 +02:00

5.5 KiB
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mtfsb0x — Move to FPSCR Bit 0

Category: Control / CR / SPR · Form: X · Opcode: 0xfc00008c

Assembler Mnemonics

Mnemonic XML entry Flags Description
mtfsb0 mtfsb0x — Move to FPSCR Bit 0
mtfsb0. mtfsb0x Rc=1 Move to FPSCR Bit 0

Syntax

mtfsb0[Rc] [FPSCRD]

Encoding

mtfsb0x — form X

  • Opcode word: 0xfc00008c
  • Primary opcode (bits 0–5): 63
  • Extended opcode: 70
  • Synchronising: no
Bits Field Meaning
0–5 OPCD primary opcode
6–10 RT/FRT/VRT destination
11–15 RA/FRA/VRA source A
16–20 RB/FRB/VRB source B
21–30 XO extended opcode (10 bits)
31 Rc record-form flag

Operands

Field Role Description
FPSCRD mtfsb0x: write FPSCR destination field.
CR mtfsb0x: write (conditional) Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mtfsb0x

  • Reads (always): none
  • Reads (conditional): none
  • Writes (always): FPSCRD
  • Writes (conditional): CR

Status-Register Effects

  • mtfsb0x: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtfsb0x

Canary emitter (frozen snapshot @ f21ebd49e9) 
int InstrEmit_mtfsb0x(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}

Special Cases & Edge Conditions

  • Operation. Clears (sets to 0) a single named bit of the 32-bit FPSCR. The bit is selected by FPSCRD (a 5-bit absolute index 0..31, big-endian: 0 = MSB = FX).
  • The mnemonic name "Bit 0" is misleading. "0" refers to the value being written, not to bit position 0. Pair with mtfsb1x which writes a 1.
  • Restricted bits. Per PowerISA, mtfsb0 cannot clear bits 1 (FEX) or 2 (VX) — those are summary bits, derived from other FPSCR bits. xenia-rs does not enforce this restriction; it will happily flip any bit. In practice no Xbox 360 title relies on the restriction's enforcement.
  • Rc=1. mtfsb0. (Rc=1) updates CR1 with the high four FPSCR bits (FX, FEX, VX, OX) after the clear. This is the FPU's record-form analogue.
  • Common use. Reset a sticky exception bit ahead of a sequence of FP ops you want to monitor (e.g. mtfsb0 5 to clear ZX before a divide series, then read it back).
  • xenia simplification. xenia-rs maintains FPSCR as a u32 and does the bit clear correctly, but most downstream FP instructions in xenia do not update FPSCR exception bits — so monitoring them after mtfsb0 will see the bits stay at their seed value. Acceptable for titles that use FPSCR only to manage rounding / non-exception state.
  • Not synchronising. Reorderable.

Related Instructions

  • mtfsb1x — set a single FPSCR bit to 1.
  • mtfsfx — write fields of FPSCR from an FPR.
  • mtfsfix — write a 4-bit immediate into one FPSCR field.
  • mffsx — read FPSCR.
  • mcrfs — copy FPSCR field → CR field (and clear sticky bits).

mtfsb0 is itself the simplified form (Rc=0); mtfsb0. is the recording variant.

IBM Reference

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