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dedcf37867ce3a51f00e90aef2ac2948e3eab76b
Sylpheed/tools/ppc-manual/control/mtmsrd.md
sim dedcf37867 docs(ppc-manual): quote Canary and our own decoder, not the retired xenia-rs 
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.

What each source contributed, measured on the 350 pages before this change:

  Operation (pseudocode)  251 pages: fixed boilerplate "derives from the xenia-rs
                          interpreter"; 99 carry real hand-written seeds
  C translation           337 pages: the same kind of boilerplate
  xenia-rs snapshot       336 pages: the interpreter arm, pasted in — the only
                          per-instruction semantics on unseeded pages
  links                   xenia-rs opcode/decoder/interpreter + Canary emitter

Now:

  * semantics come from **Xenia Canary**, the reference emulator, read through
    `git show` at a pinned upstream commit (`origin/canary_experimental`,
    f21ebd49e9). Not our checkout: it carries instrumentation and lacked
    upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
    Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
    one-line delegations also the helper that holds the semantics.
  * decode references point at `crates/sylpheed-ppc` — the decoder that
    produces `sylpheed.db` — as in-repo relative links.
  * the boilerplate now says what is true, and the C translation guide maps
    Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
    that `UpdateCR(n, v)` truncates to 32 bits).
  * `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
    missing sources are now errors, not empty results.

Verified:

  consistency checks        455 XML entries, 350 families, 598 index keys
  hand-written tails        386/386 byte-identical after regeneration
  xenia-rs in generated     0
  pages with a snapshot     349/350 (was 336) — `dcbi` has no Canary emitter at all
  in-repo decoder links     910/910 resolve to a line holding the identifier
  emitter boundaries        brace counter == column-0 `}` rule on 521/521;
                            preprocessor model unit-tested (#if 0/#else/#elif)
  idempotency               re-run: 0 pages updated, 0 working-tree changes

Hand-written notes (outside the generated regions) are not rewritten here:

  * 110 links into `../../xenia-rs/...` were dead; they now point at the file in
    the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
    were dropped because the notes predate that commit — 0 of 441 old line
    ranges match it — and a precise-looking wrong anchor is worse than none. The
    link text, which carries the author's line numbers, is unchanged.
  * 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
    for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
    114 need checking one by one, and some invert — e.g. `divdx` notes a correct
    64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
    a deliberate pass rather than a blind substitution.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 20:34:34 +02:00

5.5 KiB
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mtmsrd — Move to Machine State Register Doubleword

Category: Control / CR / SPR · Form: X · Opcode: 0x7c000164 · sync

Assembler Mnemonics

Mnemonic XML entry Flags Description
mtmsrd mtmsrd — Move to Machine State Register Doubleword

Syntax

mtmsrd [RS]

Encoding

mtmsrd — form X

  • Opcode word: 0x7c000164
  • Primary opcode (bits 0–5): 31
  • Extended opcode: 178
  • Synchronising: yes
Bits Field Meaning
0–5 OPCD primary opcode
6–10 RT/FRT/VRT destination
11–15 RA/FRA/VRA source A
16–20 RB/FRB/VRB source B
21–30 XO extended opcode (10 bits)
31 Rc record-form flag

Operands

Field Role Description
RS mtmsrd: read Source GPR (alias for RD in some stores).
MSR mtmsrd: write Machine State Register.

Register Effects

mtmsrd

  • Reads (always): RS
  • Reads (conditional): none
  • Writes (always): MSR
  • Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtmsrd

Canary emitter (frozen snapshot @ f21ebd49e9) 
int InstrEmit_mtmsrd(PPCHIRBuilder& f, const InstrData& i) {
  // todo: this is moving msr under a mask, so only writing EE and RI

  Value* from = f.LoadGPR(i.X.RT);
  Value* mtmsrd_mask = f.LoadConstantUint64((1ULL << 15));
  Value* msr = f.LoadContext(offsetof(PPCContext, msr), INT64_TYPE);

  Value* new_msr = f.Or(f.And(from, mtmsrd_mask), f.AndNot(msr, mtmsrd_mask));

  f.StoreContext(offsetof(PPCContext, msr), new_msr);
  return 0;
}

Special Cases & Edge Conditions

  • Privileged. Like mtmsr, supervisor-only. Game code never emits it.
  • 64-bit form. Writes all 64 MSR bits — including MSR[SF] (bit 0) which selects 64-bit mode, MSR[HV] (bit 3, hypervisor), MSR[EE] (32, external interrupts), MSR[PR] (33, problem state), MSR[FP] (34), MSR[ME] (35, machine-check enable), MSR[DR]/MSR[IR] (data/instruction translation, 38/39), MSR[RI] (63, recoverable interrupt). On the Xenon kernel this is the canonical MSR-write instruction.
  • L operand. Same L-bit selector as mtmsr: L=1 updates only MSR[EE] and MSR[RI]; L=0 updates the full register. xenia-rs ignores L and always writes the full doubleword (matching the typical kernel use).
  • Synchronisation. Marked sync — execution-synchronising. PowerISA recommends isync afterwards if subsequent fetch / data semantics depend on the new MSR.
  • xenia model. Shares one interpreter arm with mtmsr: ctx.msr = ctx.gpr[rs]. No architectural side effects beyond writing the storage; no privilege check.
  • No CR / XER updates.
  • Used in interrupt return paths. Kernel handlers commonly write SRR1 (saved MSR) into MSR via mtmsrd followed by rfid to atomically restore state and jump to SRR0.

Related Instructions

  • mfmsr — read MSR.
  • mtmsr — 32-bit form (low half only).
  • sc — kernel entry; the kernel typically pairs mtmsrd + rfid to return.

mtmsrd has no simplified mnemonics.

IBM Reference

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