Sylpheed/tools/ppc-manual/memory/std.md

std — Store Doubleword

Category: Memory · Form: DS · Opcode: 0xf8000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
std	std	—	Store Doubleword
stdu	stdu	—	Store Doubleword with Update
stdux	stdux	—	Store Doubleword with Update Indexed
stdx	stdx	—	Store Doubleword Indexed

Syntax

std [RS], [ds]([RA0])
stdu [RS], [ds]([RA])
stdux [RS], [RA], [RB]
stdx [RS], [RA0], [RB]

Encoding

std — form DS

• Opcode word: 0xf8000000
• Primary opcode (bits 0–5): 62
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS)
11–15	RA	source GPR (0 ⇒ literal 0)
16–29	DS	14-bit signed word-scaled displacement
30–31	XO	extended opcode

stdu — form DS

• Opcode word: 0xf8000001
• Primary opcode (bits 0–5): 62
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS)
11–15	RA	source GPR (0 ⇒ literal 0)
16–29	DS	14-bit signed word-scaled displacement
30–31	XO	extended opcode

stdux — form X

• Opcode word: 0x7c00016a
• Primary opcode (bits 0–5): 31
• Extended opcode: 181
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stdx — form X

• Opcode word: 0x7c00012a
• Primary opcode (bits 0–5): 31
• Extended opcode: 149
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	std: read; stdu: read; stdux: read; stdx: read	Source GPR (alias for RD in some stores).
RA	std: read; stdu: read; stdu: write; stdux: read; stdux: write	Source GPR (r0–r31).
ds	std: read; stdu: read	14-bit signed word-aligned displacement (DS << 2).
RB	stdux: read; stdx: read	Source GPR.
RA0	stdx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.

Register Effects

std

• Reads (always): RS, RA, ds
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stdu

• Reads (always): RS, RA, ds
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

stdux

• Reads (always): RS, RA, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

stdx

• Reads (always): RS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(ds || 0b00)
MEM(EA, 8) <- (RS)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

std

• Canary XML: tools/ppc-instructions.xml — search for mnem="std"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:575
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:230
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:514

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_std(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + EXTS(DS || 0b00)
  // MEM(EA, 8) <- (RS)
  Value* b;
  if (i.DS.RA == 0) {
    b = f.LoadZeroInt64();
  } else {
    b = f.LoadGPR(i.DS.RA);
  }

  Value* offset = f.LoadConstantInt64(XEEXTS16(i.DS.DS << 2));
  f.StoreOffset(b, offset, f.ByteSwap(f.LoadGPR(i.DS.RT)));
  return 0;
}

stdu

• Canary XML: tools/ppc-instructions.xml — search for mnem="stdu"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:594
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:233
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:515

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stdu(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + EXTS(DS || 0b00)
  // MEM(EA, 8) <- (RS)
  // RA <- EA
  Value* ea = CalculateEA_i(f, i.DS.RA, XEEXTS16(i.DS.DS << 2));
  f.Store(ea, f.ByteSwap(f.LoadGPR(i.DS.RT)));
  StoreEA(f, i.DS.RA, ea);
  return 0;
}

stdux

• Canary XML: tools/ppc-instructions.xml — search for mnem="stdux"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:604
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:234
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:901

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stdux(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // MEM(EA, 8) <- (RS)
  // RA <- EA
  Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
  f.Store(ea, f.ByteSwap(f.LoadGPR(i.X.RT)));
  StoreEA(f, i.X.RA, ea);
  return 0;
}

stdx

• Canary XML: tools/ppc-instructions.xml — search for mnem="stdx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:614
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:235
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:896

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stdx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // MEM(EA, 8) <- (RS)
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  f.Store(ea, f.ByteSwap(f.LoadGPR(i.X.RT)));
  return 0;
}

Special Cases & Edge Conditions

• DS-form, not D-form. Like ld, std uses a 14-bit signed displacement scaled by 4 (EXTS(ds || 0b00)). Bits 30–31 are the extended opcode used to distinguish std (XO=0) from stdu (XO=1). Assemblers verify the byte displacement is a multiple of 4.
• Big-endian write. The 64-bit value of RS is written most-significant-byte-first: RS[0:7] to EA, RS[56:63] to EA+7. Xenia's mem.write_u64 performs the host-side byte swap if needed.
• RA0 for std and stdx. When RA = 0, base is the literal zero. Update forms stdu / stdux invoke RA = 0 as an invalid form (no RA = RS collision possible — RS and RA are independent encoding fields, and even if equal the store reads RS first).
• Update-form post-write. stdu / stdux write EA to RA after the store. Order is store-then-update.
• Alignment. Xenon tolerates unaligned doubleword stores. PowerISA permits implementations to raise alignment exceptions; portable code keeps doublewords 8-byte aligned. Cache-inhibited storage may force alignment.
• Cache-line behaviour. A doubleword store fits inside one Xenon cache line (128 B), so it's a single line write. A doubleword store that straddles a line boundary triggers two line accesses — keep doublewords 8-byte aligned to avoid the cost.
• 64-bit pointer / counter stores. Xbox 360 user code is 32-bit, but kernel structures, TOC entries, and 64-bit counters are stored with std.

Related Instructions

• stw, sth, stb — narrower integer stores.
• stdbrx — byte-reversed doubleword store.
• stdcx — store-conditional (the doubleword reservation pair end).
• ld, ldu, ldx, ldux — corresponding loads.
• stfd — FP doubleword store (same width, different register file).

IBM Reference

• AIX 7.3 — std (Store Doubleword)
• AIX 7.3 — stdu / stdx / stdux