21161154d1
- Category pages linked each family as `<slug>.md`, relative to categories/, where no family page lives. They now link `../<category>/<slug>.md`. - Form pages linked a member into its *own* category directory, so every VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is under vmx/. They now link into the family's directory. - Hand-written "Related" and sibling mentions linked other categories' pages as if they were in the same directory. 109 are retargeted through the page index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and 6 naming instructions the manual has no page for are plain text now. Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and re-pinning belongs in its own change. The generator reports 0 family pages changed and is idempotent; the only dead links left are TEMPLATE.md's placeholders. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
160 lines
6.4 KiB
Markdown
160 lines
6.4 KiB
Markdown
# `cmp` — Compare
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> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c000000`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `cmp` | `cmp` | — | Compare |
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## Syntax
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```asm
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cmp [CRFD], [L], [RA], [RB]
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```
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## Encoding
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### `cmp` — form `X`
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- **Opcode word:** `0x7c000000`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `0`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `L` | cmp: read | Operand-length bit for compare instructions (`0 ⇒ 32-bit`, `1 ⇒ 64-bit`). |
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| `RA` | cmp: read | Source GPR (`r0`–`r31`). |
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| `RB` | cmp: read | Source GPR. |
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| `CRFD` | cmp: write | CR destination field (`crf`, 0–7). |
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## Register Effects
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### `cmp`
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- **Reads (always):** `L`, `RA`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `CRFD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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if L = 0 then a,b <- EXTS((RA)[32:63]), EXTS((RB)[32:63])
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else a,b <- (RA), (RB)
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CR[BF] <- signed_compare(a, b) || XER[SO]
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`cmp`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="cmp"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:523`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_alu.cc#L523)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:27`](../../../crates/sylpheed-ppc/src/opcode.rs#L27)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:864`](../../../crates/sylpheed-ppc/src/decoder.rs#L864)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_cmp(PPCHIRBuilder& f, const InstrData& i) {
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// if L = 0 then
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// a <- EXTS((RA)[32:63])
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// b <- EXTS((RB)[32:63])
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// else
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// a <- (RA)
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// b <- (RB)
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// if a < b then
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// c <- 0b100
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// else if a > b then
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// c <- 0b010
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// else
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// c <- 0b001
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// CR[4×BF+32:4×BF+35] <- c || XER[SO]
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uint32_t BF = i.X.RT >> 2;
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uint32_t L = i.X.RT & 1;
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Value* lhs;
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Value* rhs;
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if (L) {
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lhs = f.LoadGPR(i.X.RA);
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rhs = f.LoadGPR(i.X.RB);
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} else {
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lhs = f.Truncate(f.LoadGPR(i.X.RA), INT32_TYPE);
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rhs = f.Truncate(f.LoadGPR(i.X.RB), INT32_TYPE);
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}
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f.UpdateCR(BF, lhs, rhs);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Extended Pseudocode
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```
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if L = 0 then ; 32-bit compare
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a <- EXTS((RA)[32:63]) ; sign-extend low word to 64
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b <- EXTS((RB)[32:63])
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else ; 64-bit compare
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a <- (RA)
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b <- (RB)
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CR[BF] <- { LT: a <s b, GT: a >s b, EQ: a = b, SO: XER[SO] } ; signed
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```
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## Special Cases & Edge Conditions
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- **`BF` is a CR field (0–7), not a bit.** The `crfD` operand encodes which of the eight 4-bit CR fields is updated. Assemblers write it as `crN` where `N ∈ 0..7`. The simplified mnemonic `cmpw RA, RB` ≡ `cmp cr0, 0, RA, RB` is universal in Xbox 360 code.
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- **`L` bit selects width.** `L = 0` (the usual `cmpw` / `cmpd`-is-rare path) performs a *32-bit* signed compare of `RA[32:63]` and `RB[32:63]`, both sign-extended to 64 bits. `L = 1` (`cmpd`) performs a full 64-bit signed compare.
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- **Signed.** Use [`cmpl`](cmpl.md) / [`cmpli`](cmpli.md) for unsigned comparisons. Confusing signed/unsigned is the most common compare-family bug in hand-written asm.
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- **SO is always copied from `XER[SO]`.** This makes overflow observable across arithmetic/compare sequences: an `addo.` followed by `beq` can branch on the record-form flag while `bso` can inspect the sticky overflow.
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- **`cr0` is the default for record-form ALU**; by convention assemblers and generators reserve `cr0` for the chain of `Rc=1` instructions and use `cr1..cr7` (or `cmp` to an explicit field) for standalone compares. Don't assume `cmp` writes `cr0` unless the `BF` operand says so.
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- **No register is written** beyond the 4-bit CR field. `cmp` has no `Rc` or `OE` bit.
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- **Canary is one direct compare.** `L` selects either the full 64-bit operands or both truncated to `INT32`, then `f.UpdateCR(BF, lhs, rhs)` sets `LT`/`GT`/`EQ` from a single signed comparison. ⚠️ It never writes the field's `SO` bit — spec copies `XER[SO]` into it — so Canary leaves `SO` holding whatever was there before.
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## Related Instructions
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- [`cmpi`](cmpi.md) — signed compare against a 16-bit immediate.
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- [`cmpl`](cmpl.md), [`cmpli`](cmpli.md) — unsigned versions.
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- [`cmpw`](cmp.md), [`cmpd`](cmp.md) — simplified mnemonics selecting `L`.
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- [`mcrxr`](../control/mcrxr.md) — move `XER[SO..CA]` into a CR field and clear them; used to reset sticky overflow.
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- Every `Rc=1` ALU instruction ([`addx`](addx.md), [`subfx`](subfx.md), [`andx`](andx.md), …) — these implicitly perform a signed-compare-to-zero into `cr0`; use explicit `cmp` only when comparing two non-zero values or using a non-zero CR field.
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## IBM Reference
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- [AIX 7.3 — `cmp` (Compare)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-cmp-compare-instruction)
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- [AIX 7.3 — `cmpw` / `cmpd` (simplified mnemonics)](https://www.ibm.com/docs/en/aix/7.3.0?topic=mnemonics-cmpw-compare-word)
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