Sylpheed/tools/ppc-manual/alu/cntlzdx.md

cntlzdx — Count Leading Zeros Doubleword

Category: Integer ALU · Form: X · Opcode: 0x7c000074

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
cntlzd	cntlzdx	—	Count Leading Zeros Doubleword
cntlzd.	cntlzdx	Rc=1	Count Leading Zeros Doubleword

Syntax

cntlzd [RA], [RS]

Encoding

cntlzdx — form X

• Opcode word: 0x7c000074
• Primary opcode (bits 0–5): 31
• Extended opcode: 58
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	cntlzdx: read	Source GPR (alias for RD in some stores).
RA	cntlzdx: write	Source GPR (r0–r31).
CR	cntlzdx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

cntlzdx

• Reads (always): RS
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• cntlzdx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

n <- number_of_leading_zero_bits((RS))           ; n in 0..64
RA <- zero_extend(n)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

cntlzdx

• Canary XML: tools/ppc-instructions.xml — search for mnem="cntlzdx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:674
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:32
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:882

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_cntlzdx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- 0
  // do while n < 64
  //   if (RS)[n] = 1 then leave n
  //   n <- n + 1
  // RA <- n
  Value* v = f.CountLeadingZeros(f.LoadGPR(i.X.RT));
  v = f.ZeroExtend(v, INT64_TYPE);
  f.StoreGPR(i.X.RA, v);
  if (i.X.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• Result range is 0..=64. When RS == 0, every bit is a leading zero and RA = 64. When the high bit (RS[0]) is set, RA = 0. Any intermediate value yields the count of high-order zeros before the first 1-bit.
• Counts across the full 64 bits. Use cntlzwx when you only want to count the low 32 bits.
• Useful as floor(log2(x)) = 63 − cntlzd(x) for nonzero x. Frequently used in fast normalization, priority encoders, and bit-vector operations.
• RB field unused. This is X-form but only RS is read; RB is a placeholder slot.
• Rc=1 CR0 is never LT. The count is 0–64, so Canary's INT32-truncating f.UpdateCR(0, v) loses nothing: EQ exactly when RS[0] == 1 (count 0), otherwise GT. EQ therefore means "high bit set in RS" — a one-instruction sign test for negative-as-signed values.
• No XER side effects. Counts neither overflow nor carry.

Related Instructions

• cntlzwx — 32-bit version (counts only RS[32:63]).
• sldx, srdx — pair with cntlzd for normalisation.
• rldiclx — for extracting individual bit positions once the leading-zero count is known.
• cmpi / cmp — alternative for testing the high bit.

IBM Reference

• AIX 7.3 — cntlzd (Count Leading Zeros Doubleword)