Sylpheed/tools/ppc-manual/alu/cmp.md

cmp — Compare

Category: Integer ALU · Form: X · Opcode: 0x7c000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
cmp	cmp	—	Compare

Syntax

cmp [CRFD], [L], [RA], [RB]

Encoding

cmp — form X

• Opcode word: 0x7c000000
• Primary opcode (bits 0–5): 31
• Extended opcode: 0
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
L	cmp: read	Operand-length bit for compare instructions (0 ⇒ 32-bit, 1 ⇒ 64-bit).
RA	cmp: read	Source GPR (r0–r31).
RB	cmp: read	Source GPR.
CRFD	cmp: write	CR destination field (crf, 0–7).

Register Effects

cmp

• Reads (always): L, RA, RB
• Reads (conditional): none
• Writes (always): CRFD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

if L = 0 then a,b <- EXTS((RA)[32:63]), EXTS((RB)[32:63])
else             a,b <- (RA), (RB)
CR[BF] <- signed_compare(a, b) || XER[SO]

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

cmp

• Canary XML: tools/ppc-instructions.xml — search for mnem="cmp"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:523
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:27
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:864

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_cmp(PPCHIRBuilder& f, const InstrData& i) {
  // if L = 0 then
  //   a <- EXTS((RA)[32:63])
  //   b <- EXTS((RB)[32:63])
  // else
  //   a <- (RA)
  //   b <- (RB)
  // if a < b then
  //   c <- 0b100
  // else if a > b then
  //   c <- 0b010
  // else
  //   c <- 0b001
  // CR[4×BF+32:4×BF+35] <- c || XER[SO]
  uint32_t BF = i.X.RT >> 2;
  uint32_t L = i.X.RT & 1;
  Value* lhs;
  Value* rhs;
  if (L) {
    lhs = f.LoadGPR(i.X.RA);
    rhs = f.LoadGPR(i.X.RB);
  } else {
    lhs = f.Truncate(f.LoadGPR(i.X.RA), INT32_TYPE);
    rhs = f.Truncate(f.LoadGPR(i.X.RB), INT32_TYPE);
  }
  f.UpdateCR(BF, lhs, rhs);
  return 0;
}

Extended Pseudocode

if L = 0 then                                   ; 32-bit compare
    a <- EXTS((RA)[32:63])                      ; sign-extend low word to 64
    b <- EXTS((RB)[32:63])
else                                            ; 64-bit compare
    a <- (RA)
    b <- (RB)
CR[BF] <- { LT: a <s b, GT: a >s b, EQ: a = b, SO: XER[SO] }   ; signed

Special Cases & Edge Conditions

• BF is a CR field (0–7), not a bit. The crfD operand encodes which of the eight 4-bit CR fields is updated. Assemblers write it as crN where N ∈ 0..7. The simplified mnemonic cmpw RA, RB ≡ cmp cr0, 0, RA, RB is universal in Xbox 360 code.
• L bit selects width. L = 0 (the usual cmpw / cmpd-is-rare path) performs a 32-bit signed compare of RA[32:63] and RB[32:63], both sign-extended to 64 bits. L = 1 (cmpd) performs a full 64-bit signed compare.
• Signed. Use cmpl / cmpli for unsigned comparisons. Confusing signed/unsigned is the most common compare-family bug in hand-written asm.
• SO is always copied from XER[SO]. This makes overflow observable across arithmetic/compare sequences: an addo. followed by beq can branch on the record-form flag while bso can inspect the sticky overflow.
• cr0 is the default for record-form ALU; by convention assemblers and generators reserve cr0 for the chain of Rc=1 instructions and use cr1..cr7 (or cmp to an explicit field) for standalone compares. Don't assume cmp writes cr0 unless the BF operand says so.
• No register is written beyond the 4-bit CR field. cmp has no Rc or OE bit.
• Canary is one direct compare. L selects either the full 64-bit operands or both truncated to INT32, then f.UpdateCR(BF, lhs, rhs) sets LT/GT/EQ from a single signed comparison. ⚠️ It never writes the field's SO bit — spec copies XER[SO] into it — so Canary leaves SO holding whatever was there before.

Related Instructions

• cmpi — signed compare against a 16-bit immediate.
• cmpl, cmpli — unsigned versions.
• cmpw, cmpd — simplified mnemonics selecting L.
• mcrxr — move XER[SO..CA] into a CR field and clear them; used to reset sticky overflow.
• Every Rc=1 ALU instruction (addx, subfx, andx, …) — these implicitly perform a signed-compare-to-zero into cr0; use explicit cmp only when comparing two non-zero values or using a non-zero CR field.

IBM Reference

• AIX 7.3 — cmp (Compare)
• AIX 7.3 — cmpw / cmpd (simplified mnemonics)