Sylpheed/tools/ppc-manual/vmx/vadduhm.md

vadduhm — Vector Add Unsigned Half Word Modulo

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000040

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vadduhm	vadduhm	—	Vector Add Unsigned Half Word Modulo

Syntax

vadduhm [VD], [VA], [VB]

Encoding

vadduhm — form VX

• Opcode word: 0x10000040
• Primary opcode (bits 0–5): 4
• Extended opcode: 64
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vadduhm: read	Source A vector register.
VB	vadduhm: read	Source B vector register.
VD	vadduhm: write	Destination vector register.

Register Effects

vadduhm

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vadduhm

• Canary XML: tools/ppc-instructions.xml — search for mnem="vadduhm"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:387
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:303
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:556

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vadduhm(PPCHIRBuilder& f, const InstrData& i) {
  Value* v = f.VectorAdd(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT16_TYPE,
                         ARITHMETIC_UNSIGNED);
  f.StoreVR(i.VX.VD, v);
  return 0;
}

Special Cases & Edge Conditions

• Eight half-word lanes. VD[i] = (VA[i] + VB[i]) mod 65536 for i = 0..7. Lane 0 (VD[0..1] after stvx) is the most-significant half.
• Modulo wrap, not saturating. Overflow silently wraps in 16-bit arithmetic; VSCR[SAT] is not touched and there is no carry-out. Sign-agnostic — modulo add for signed int16 and unsigned u16 is bit-pattern-identical, so this is also the de-facto vaddshm.
• No XER, no NJ involvement.
• Aliasing legal. vadduhm v3, v3, v4 is a single-issue accumulate.
• Pairs with saturating siblings. Switch to vadduhs for unsigned clamp at 0xFFFF or vaddshs for signed clamp at ±32767 when overflow needs to be detected via sticky VSCR[SAT].
• Common usage. Multi-precision adds composed from 16-bit lanes; UV-coordinate accumulation; per-pixel half-precision counters.
• No VMX128 sibling.

Related Instructions

• vadduhs — same width, unsigned saturating add.
• vaddshs — same width, signed saturating add.
• vaddubm, vadduwm — modulo add at byte / word width.
• vsubuhm — the matching modulo subtract.
• vavguh — unsigned half-word rounding average; useful when addition needs to stay representable.

IBM Reference

• AIX 7.3 — vadduhm (Vector Add Unsigned Half Word Modulo)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Integer Arithmetic