Sylpheed/tools/ppc-manual/vmx/vaddshs.md

vaddshs — Vector Add Signed Half Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000340

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vaddshs	vaddshs	—	Vector Add Signed Half Word Saturate

Syntax

vaddshs [VD], [VA], [VB]

Encoding

vaddshs — form VX

• Opcode word: 0x10000340
• Primary opcode (bits 0–5): 4
• Extended opcode: 832
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vaddshs: read	Source A vector register.
VB	vaddshs: read	Source B vector register.
VD	vaddshs: write	Destination vector register.
VSCR	vaddshs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vaddshs

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vaddshs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vaddshs

• Canary XML: tools/ppc-instructions.xml — search for mnem="vaddshs"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:356
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:299
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:620

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vaddshs(PPCHIRBuilder& f, const InstrData& i) {
  Value* v = f.VectorAdd(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT16_TYPE,
                         ARITHMETIC_SATURATE);
  f.StoreSAT(f.DidSaturate(v));
  f.StoreVR(i.VX.VD, v);
  return 0;
}

Special Cases & Edge Conditions

• Eight signed-half lanes, saturating. Each VD[i] = clamp(VA[i] + VB[i], -32768, +32767) for i = 0..7, with both inputs interpreted as signed int16. Lane 0 (VD[0..1] after stvx) is the most-significant half.
• VSCR[SAT] is sticky-set if any lane clamps. Once set, it stays set until explicit clear via mtvscr. ⚠️ Canary never records SAT: its StoreSAT(DidSaturate(v)) writes a private vscr_sat byte, the x64 DID_SATURATE is a stub that always yields 0, and mfvscr reads vscr_vec, which only mtvscr changes.
• The modulo counterpart is vadduhm. Modulo add for signed and unsigned halves is bit-identical, so vadduhm covers both when wraparound is wanted; switch to vaddshs only when clipping with sign awareness is desired.
• Asymmetric clamp. +32767 + 1 = +32767; -32768 + (-1) = -32768.
• Common 16-bit DSP idiom. Audio mixing and fixed-point colour blending lean heavily on vaddshs to combine signed Q15 / Q1.15 quantities without wraparound artefacts.
• No XER side effects, no NJ involvement (this is an integer op).
• No VMX128 sibling.

Related Instructions

• vadduhs — same width, unsigned saturating add (clamps to 0..0xFFFF).
• vadduhm — same width, modulo add; sign-agnostic.
• vaddsbs, vaddsws — signed saturating add at byte / word width.
• vsubshs — the matching signed saturating subtract.
• vmhaddshs, vmhraddshs — signed-half multiply-add with saturation, common for fixed-point DSP.
• mtvscr / mfvscr — read or clear the VSCR[SAT] bit affected here.

IBM Reference

• AIX 7.3 — vaddshs (Vector Add Signed Half Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Saturating Integer Arithmetic