21161154d1
- Category pages linked each family as `<slug>.md`, relative to categories/, where no family page lives. They now link `../<category>/<slug>.md`. - Form pages linked a member into its *own* category directory, so every VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is under vmx/. They now link into the family's directory. - Hand-written "Related" and sibling mentions linked other categories' pages as if they were in the same directory. 109 are retargeted through the page index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and 6 naming instructions the manual has no page for are plain text now. Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and re-pinning belongs in its own change. The generator reports 0 family pages changed and is idempotent; the only dead links left are TEMPLATE.md's placeholders. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
129 lines
5.5 KiB
Markdown
129 lines
5.5 KiB
Markdown
# `vadduhs` — Vector Add Unsigned Half Word Saturate
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000240`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vadduhs` | `vadduhs` | — | Vector Add Unsigned Half Word Saturate |
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## Syntax
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```asm
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vadduhs [VD], [VA], [VB]
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```
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## Encoding
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### `vadduhs` — form `VX`
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- **Opcode word:** `0x10000240`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `576`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vadduhs: read | Source A vector register. |
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| `VB` | vadduhs: read | Source B vector register. |
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| `VD` | vadduhs: write | Destination vector register. |
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| `VSCR` | vadduhs: write | Vector Status and Control Register (NJ/SAT bits). |
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## Register Effects
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### `vadduhs`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`, `VSCR`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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- `vadduhs`: **VSCR[SAT]** may be stickied on saturating vector operations.
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vadduhs`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vadduhs"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:394`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L394)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:304`](../../../crates/sylpheed-ppc/src/opcode.rs#L304)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:597`](../../../crates/sylpheed-ppc/src/decoder.rs#L597)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vadduhs(PPCHIRBuilder& f, const InstrData& i) {
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Value* v = f.VectorAdd(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT16_TYPE,
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ARITHMETIC_UNSIGNED | ARITHMETIC_SATURATE);
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f.StoreSAT(f.DidSaturate(v));
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f.StoreVR(i.VX.VD, v);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Eight unsigned-half lanes, saturating.** Each `VD[i] = min(VA[i] + VB[i], 0xFFFF)` for `i = 0..7`. Lane 0 (`VD[0..1]` after `stvx`) is the most-significant half.
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- **`VSCR[SAT]` is sticky-set** if any lane clamps. Cleared only by [`mtvscr`](../control/mtvscr.md). ⚠️ Canary never records `SAT`: its `StoreSAT(DidSaturate(v))` writes a private `vscr_sat` byte, the x64 `DID_SATURATE` is a stub that always yields 0, and [`mfvscr`](../control/mfvscr.md) reads `vscr_vec`, which only `mtvscr` changes.
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- **One-sided clamp.** Unsigned add cannot underflow, so only the upper bound `0xFFFF` ever clips.
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- **The modulo counterpart is `vadduhm`.** Use `vadduhs` when "too large to fit" must be flagged or clipped — typical for accumulating Q16 unsigned counters.
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- **No XER side effects.**
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- **Maps directly to `_mm_adds_epu16`** on SSE2 hosts — semantically identical for the lanes. Canary emits a saturating unsigned `VectorAdd` but never records `VSCR[SAT]` (x64 `DID_SATURATE` is a stub).
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- **No VMX128 sibling.**
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## Related Instructions
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- [`vadduhm`](vadduhm.md) — same width, modulo (non-saturating) add.
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- [`vaddshs`](vaddshs.md) — same width, signed saturating add (range `-32768..+32767`).
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- [`vaddubs`](vaddubs.md), [`vadduws`](vadduws.md) — unsigned saturating add at byte / word width.
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- [`vsubuhs`](vsubuhs.md) — the matching unsigned saturating subtract.
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- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear the sticky `VSCR[SAT]` bit.
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## IBM Reference
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- [AIX 7.3 — `vadduhs` (Vector Add Unsigned Half Word Saturate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vadduhs-vector-add-unsigned-half-word-saturate-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Saturating Integer Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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