Sylpheed/tools/ppc-manual/vmx/vctsxs.md

vctsxs — Vector Convert to Signed Fixed-Point Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x100003ca

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vctsxs	vctsxs	—	Vector Convert to Signed Fixed-Point Word Saturate

Syntax

vctsxs [VD], [VB], [UIMM]

Encoding

vctsxs — form VX

• Opcode word: 0x100003ca
• Primary opcode (bits 0–5): 4
• Extended opcode: 970
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VB	vctsxs: read	Source B vector register.
UIMM	vctsxs: read	16-bit unsigned immediate. Zero-extended.
VD	vctsxs: write	Destination vector register.
VSCR	vctsxs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vctsxs

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vctsxs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vctsxs

• Canary XML: tools/ppc-instructions.xml — search for mnem="vctsxs"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:536
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:340
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:632

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vctsxs(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vctsxs_(f, i.VX.VD, i.VX.VB, i.VX.VA);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:525) ──
int InstrEmit_vctsxs_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb,
                      uint32_t uimm) {
  // (VD) <- int_sat(VB as signed * 2^uimm)
  float fuimm = static_cast<float>(std::exp2(uimm));
  Value* v =
      f.Mul(f.LoadVR(vb), f.Splat(f.LoadConstantFloat32(fuimm), VEC128_TYPE));
  v = f.VectorConvertF2I(v);
  f.StoreSAT(f.DidSaturate(v));
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Convert IEEE float lane to signed-Q int32, saturating. For each of the four word lanes, VD[i] = clamp(round_toward_zero(VB[i] * 2^UIMM), INT32_MIN, INT32_MAX). The 5-bit UIMM (bits 11..15) gives the Q-format fractional shift, in 0..31.
• Saturating, not wrapping. Out-of-range floats clamp to INT32_MIN (negative overflow) or INT32_MAX (positive overflow) — not the wrap-around behaviour of x86 cvttps2dq (which produces 0x80000000 on overflow regardless of sign). Canary converts with vcvttps2dq and then blends INT32_MAX into lanes that overflowed from a non-negative input.
• NaN → 0 in Canary. It masks NaN lanes to 0 (vcmpunordps + vpandn). Some references state "NaN → INT32_MIN" for hardware; which one Xenon does is unverified. Canary never records VSCR[SAT].
• VSCR[SAT] is sticky-set if any lane saturates (overflow or NaN). Cleared only by mtvscr.
• Rounding is truncate-toward-zero. Always; no per-instruction rounding control.
• VSCR[NJ] flushes denormal inputs to zero before scaling (Xenon default).
• Big-endian word lanes. Lane 0 is the most-significant word.
• No XER changes, no traps.
• No VMX128 sibling.
• Inverse of vcfsx, but the inverse direction saturates rather than wraps — round-trips lose the magnitude of out-of-range values.

Related Instructions

• vctuxs — same shape, unsigned destination.
• vcfsx, vcfux — inverse direction (int → float with Q-shift).
• vrfin, vrfip, vrfim, vrfiz — float-to-float rounding modes (round-to-nearest, up, down, toward-zero) when staying in float.
• mtvscr / mfvscr — read or clear VSCR[SAT].

IBM Reference

• AIX 7.3 — vctsxs (Vector Convert to Signed Fixed-Point Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Conversion Instructions