21161154d1
- Category pages linked each family as `<slug>.md`, relative to categories/, where no family page lives. They now link `../<category>/<slug>.md`. - Form pages linked a member into its *own* category directory, so every VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is under vmx/. They now link into the family's directory. - Hand-written "Related" and sibling mentions linked other categories' pages as if they were in the same directory. 109 are retargeted through the page index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and 6 naming instructions the manual has no page for are plain text now. Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and re-pinning belongs in its own change. The generator reports 0 family pages changed and is idempotent; the only dead links left are TEMPLATE.md's placeholders. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
6.6 KiB
6.6 KiB
vrfin — Vector Round to Floating-Point Integer Nearest
Category: VMX (Altivec) · Form: VX · Opcode:
0x1000020a
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
vrfin |
vrfin |
— | Vector Round to Floating-Point Integer Nearest |
vrfin128 |
vrfin128 |
— | Vector128 Round to Floating-Point Integer Nearest |
Syntax
vrfin [VD], [VB]
vrfin128 [VD], [VB]
Encoding
vrfin — form VX
- Opcode word:
0x1000020a - Primary opcode (bits 0–5):
4 - Extended opcode:
522 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (4) |
| 6–10 | VRT/VD |
destination vector register |
| 11–15 | VRA/VA |
source A vector register |
| 16–20 | VRB/VB |
source B vector register |
| 21–31 | XO |
extended opcode (11 bits) |
vrfin128 — form VX128_3
- Opcode word:
0x18000370 - Primary opcode (bits 0–5):
6 - Extended opcode:
880 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (6) |
| 6–10 | VD128l |
destination low 5 bits |
| 11–15 | IMM |
5-bit immediate |
| 16–20 | VB128l |
source B low 5 bits |
| 21–27 | XO |
extended opcode |
| 28–29 | VD128h |
destination high 2 bits |
| 30–31 | VB128h |
source B high 2 bits |
Operands
| Field | Role | Description |
|---|---|---|
VB |
vrfin: read; vrfin128: read | Source B vector register. |
VD |
vrfin: write; vrfin128: write | Destination vector register. |
Register Effects
vrfin
- Reads (always):
VB - Reads (conditional): none
- Writes (always):
VD - Writes (conditional): none
vrfin128
- Reads (always):
VB - Reads (conditional): none
- Writes (always):
VD - Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
C Translation Example
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
vrfin
- Canary XML:
tools/ppc-instructions.xml— search formnem="vrfin" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:1229 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:425 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:594
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_vrfin(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_vrfin_(f, i.VX.VD, i.VX.VB);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1223) ──
int InstrEmit_vrfin_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
// (VD) <- RoundToNearest(VB)
Value* v = f.Round(f.LoadVR(vb), ROUND_TO_NEAREST);
f.StoreVR(vd, v);
return 0;
}
vrfin128
- Canary XML:
tools/ppc-instructions.xml— search formnem="vrfin128" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:1232 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:426 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:776
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_vrfin128(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_vrfin_(f, VX128_3_VD128, VX128_3_VB128);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1223) ──
int InstrEmit_vrfin_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
// (VD) <- RoundToNearest(VB)
Value* v = f.Round(f.LoadVR(vb), ROUND_TO_NEAREST);
f.StoreVR(vd, v);
return 0;
}
Special Cases & Edge Conditions
- Round to nearest integer. Each 32-bit float lane of
VBis rounded to the nearest representable integer value, ties to even on Xenon. Canary emitsvroundpswith rounding mode 0, which is round-half-to-even — a match. - IEEE-754 binary32 output;
VSCR[NJ]honoured. - Integer-too-big lanes are no-ops (|x| ≥ 2²³).
- NaN and ±∞ pass through unchanged.
- No VSCR[SAT], no FPSCR update.
- Big-endian lane indexing.
- VMX128 sibling
vrfin128.
Related Instructions
vrfim— round toward −∞.vrfip— round toward +∞.vrfiz— round toward zero.vctsxs,vctuxs— float → fixed-point integer.