Sylpheed/tools/ppc-manual/vmx/vmsumshs.md

vmsumshs — Vector Multiply-Sum Signed Half Word Saturate

Category: VMX (Altivec) · Form: VA · Opcode: 0x10000029

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmsumshs	vmsumshs	—	Vector Multiply-Sum Signed Half Word Saturate

Syntax

vmsumshs [VD], [VA], [VB], [VC]

Encoding

vmsumshs — form VA

• Opcode word: 0x10000029
• Primary opcode (bits 0–5): 4
• Extended opcode: 41
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21–25	VRC	source C / shift
26–31	XO	extended opcode (6 bits)

Operands

Field	Role	Description
VA	vmsumshs: read	Source A vector register.
VB	vmsumshs: read	Source B vector register.
VC	vmsumshs: read	Source C vector register / 3-bit selector.
VD	vmsumshs: write	Destination vector register.
VSCR	vmsumshs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vmsumshs

• Reads (always): VA, VB, VC
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vmsumshs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmsumshs

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmsumshs"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1034
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:381
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:699

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmsumshs(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}

Special Cases & Edge Conditions

• Signed half-word multiply-sum, saturating. Per word lane:

  VD[i] = clamp(VC[i] + int16(VA[2*i]) * int16(VB[2*i])
                       + int16(VA[2*i+1]) * int16(VB[2*i+1]), INT32_MIN, INT32_MAX)
  

  Two signed-half × signed-half products plus a signed-word accumulator, clamped to int32.
• Wide-then-clamp ordering. The IBM specification accumulates the full sum and clamps only the final result to int32, which avoids spurious mid-sum saturation that would happen if the products were clamped individually. ⚠️ Canary does not implement vmsumshs: its emitter is XEINSTRNOTIMPLEMENTED, so translating one logs "Unimplemented instr" and, with the default break_on_unimplemented_instructions, breaks.
• VSCR[SAT] is sticky-set if any of the four lane sums saturates. Cleared only via mtvscr.
• Big-endian half lanes. Lane 0 is the most-significant half.
• No XER, no exceptions.
• Aliasing legal.
• No VMX128 sibling.
• Common usage. High-precision dot products, audio FIR taps with overflow detection, signed-pixel filter convolution.

Related Instructions

• vmsumshm — same shape, modulo (no clamp, no SAT flag).
• vmsumuhs — unsigned half multiply-sum, saturating.
• vmsummbm, vmsumubm — multiply-sum at byte width.
• vaddsws — saturating word add for further accumulation.
• mtvscr / mfvscr — read or clear VSCR[SAT].

IBM Reference

• AIX 7.3 — vmsumshs (Vector Multiply-Sum Signed Half Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Sum Family