Sylpheed/tools/ppc-manual/vmx/vmsumuhs.md

vmsumuhs — Vector Multiply-Sum Unsigned Half Word Saturate

Category: VMX (Altivec) · Form: VA · Opcode: 0x10000027

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmsumuhs	vmsumuhs	—	Vector Multiply-Sum Unsigned Half Word Saturate

Syntax

vmsumuhs [VD], [VA], [VB], [VC]

Encoding

vmsumuhs — form VA

• Opcode word: 0x10000027
• Primary opcode (bits 0–5): 4
• Extended opcode: 39
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21–25	VRC	source C / shift
26–31	XO	extended opcode (6 bits)

Operands

Field	Role	Description
VA	vmsumuhs: read	Source A vector register.
VB	vmsumuhs: read	Source B vector register.
VC	vmsumuhs: read	Source C vector register / 3-bit selector.
VD	vmsumuhs: write	Destination vector register.
VSCR	vmsumuhs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vmsumuhs

• Reads (always): VA, VB, VC
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vmsumuhs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmsumuhs

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmsumuhs"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1049
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:384
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:697

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmsumuhs(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}

Special Cases & Edge Conditions

• Unsigned half-word multiply-sum, saturating. Per word lane:

  VD[i] = clamp(VC[i] + uint16(VA[2*i]) * uint16(VB[2*i])
                     + uint16(VA[2*i+1]) * uint16(VB[2*i+1]), 0, UINT32_MAX)
  

  Two unsigned-half × unsigned-half products plus an unsigned-word accumulator, clamped to uint32.
• Wide-then-clamp ordering. The IBM specification accumulates into a wide sum and clamps only the final result to u32. ⚠️ Canary does not implement vmsumuhs: its emitter is XEINSTRNOTIMPLEMENTED, so translating one logs "Unimplemented instr" and, with the default break_on_unimplemented_instructions, breaks.
• VSCR[SAT] is sticky-set if any lane clamps. Only the upper bound 0xFFFF_FFFF ever triggers; unsigned overflow on the low side is impossible.
• Big-endian half lanes. Lane 0 is the most-significant half.
• No XER, no exceptions.
• Aliasing legal.
• No VMX128 sibling.
• Common usage. Per-pixel summed-area calculations with overflow detection; high-precision unsigned-half FIR convolution.

Related Instructions

• vmsumuhm — same shape, modulo (no clamp, no SAT flag).
• vmsumshs — signed half multiply-sum, saturating.
• vmsumubm, vmsummbm — multiply-sum at byte width.
• vadduws — unsigned saturating word add for further accumulation.
• mtvscr / mfvscr — read or clear VSCR[SAT].

IBM Reference

• AIX 7.3 — vmsumuhs (Vector Multiply-Sum Unsigned Half Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Sum Family