Sylpheed/tools/ppc-manual/vmx/vmulesh.md

vmulesh — Vector Multiply Even Signed Half Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000348

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmulesh	vmulesh	—	Vector Multiply Even Signed Half Word

Syntax

vmulesh [VD], [VA], [VB]

Encoding

vmulesh — form VX

• Opcode word: 0x10000348
• Primary opcode (bits 0–5): 4
• Extended opcode: 840
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmulesh: read	Source A vector register.
VB	vmulesh: read	Source B vector register.
VD	vmulesh: write	Destination vector register.

Register Effects

vmulesh

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmulesh

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmulesh"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1076
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:386
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:623

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmulesh(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}

Special Cases & Edge Conditions

• Even-half signed multiply, word result. Per output word lane:

  VD[i] = int32(int16(VA[2*i]) * int16(VB[2*i]))           ; for i = 0..3
  

  Only the four even-indexed half lanes (lanes 0, 2, 4, 6 in big-endian) are read. Each int16 × int16 product is widened to int32, producing four word results.
• No saturation, no VSCR[SAT]. The full 32-bit product of two signed int16 always fits — even (-32768) * (-32768) = +1_073_741_824 is well within INT32_MAX.
• Pairs with vmulosh (odd-half sibling). Two instructions to cover all eight half lanes.
• Big-endian half indexing. Even half indices 0, 2, 4, 6 correspond to the high-order words of each word slot.
• No XER, no exceptions.
• Aliasing legal.
• No VMX128 sibling.
• Common usage. Q15 × Q15 dot products with full 32-bit precision; signed-half-coefficient FIR taps; first half of a "multiply every half lane" sequence when paired with vmulosh.

Related Instructions

• vmulosh — odd-half sibling (lanes 1, 3, 5, 7).
• vmuleuh, vmulouh — same split, unsigned.
• vmulesb, vmulosb — same family at byte width (→ half-word results).
• vmsumshm, vmsumshs — signed half multiply-sum across pairs (different shape).
• vmladduhm — per-lane modulo multiply-add (low half only).

IBM Reference

• AIX 7.3 — vmulesh (Vector Multiply Even Signed Half Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply Family