21161154d1
- Category pages linked each family as `<slug>.md`, relative to categories/, where no family page lives. They now link `../<category>/<slug>.md`. - Form pages linked a member into its *own* category directory, so every VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is under vmx/. They now link into the family's directory. - Hand-written "Related" and sibling mentions linked other categories' pages as if they were in the same directory. 109 are retargeted through the page index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and 6 naming instructions the manual has no page for are plain text now. Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and re-pinning belongs in its own change. The generator reports 0 family pages changed and is idempotent; the only dead links left are TEMPLATE.md's placeholders. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
192 lines
7.2 KiB
Markdown
192 lines
7.2 KiB
Markdown
# `vsro` — Vector Shift Right Octet
|
||
|
||
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000044c`
|
||
|
||
<!-- GENERATED: BEGIN -->
|
||
|
||
## Assembler Mnemonics
|
||
|
||
| Mnemonic | XML entry | Flags | Description |
|
||
| --- | --- | --- | --- |
|
||
| `vsro` | `vsro` | — | Vector Shift Right Octet |
|
||
| `vsro128` | `vsro128` | — | Vector128 Shift Right Octet |
|
||
|
||
## Syntax
|
||
|
||
```asm
|
||
vsro [VD], [VA], [VB]
|
||
vsro128 [VD], [VA], [VB]
|
||
```
|
||
|
||
## Encoding
|
||
|
||
### `vsro` — form `VX`
|
||
|
||
- **Opcode word:** `0x1000044c`
|
||
- **Primary opcode (bits 0–5):** `4`
|
||
- **Extended opcode:** `1100`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode (4) |
|
||
| 6–10 | `VRT/VD` | destination vector register |
|
||
| 11–15 | `VRA/VA` | source A vector register |
|
||
| 16–20 | `VRB/VB` | source B vector register |
|
||
| 21–31 | `XO` | extended opcode (11 bits) |
|
||
|
||
### `vsro128` — form `VX128`
|
||
|
||
- **Opcode word:** `0x140003d0`
|
||
- **Primary opcode (bits 0–5):** `5`
|
||
- **Extended opcode:** `976`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode (4 or 5) |
|
||
| 6–10 | `VD128l` | destination low 5 bits |
|
||
| 11–15 | `VA128l` | source A low 5 bits |
|
||
| 16–20 | `VB128l` | source B low 5 bits |
|
||
| 21 | `VA128H` | source A high bit |
|
||
| 22 | `—` | reserved |
|
||
| 23–25 | `VC` | optional VC / XO sub-field |
|
||
| 26 | `VA128h` | source A middle bit |
|
||
| 27 | `—` | reserved |
|
||
| 28–29 | `VD128h` | destination high 2 bits |
|
||
| 30–31 | `VB128h` | source B high 2 bits |
|
||
|
||
## Operands
|
||
|
||
| Field | Role | Description |
|
||
| --- | --- | --- |
|
||
| `VA` | vsro: read; vsro128: read | Source A vector register. |
|
||
| `VB` | vsro: read; vsro128: read | Source B vector register. |
|
||
| `VD` | vsro: write; vsro128: write | Destination vector register. |
|
||
|
||
## Register Effects
|
||
|
||
### `vsro`
|
||
|
||
- **Reads (always):** `VA`, `VB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `VD`
|
||
- **Writes (conditional):** _none_
|
||
|
||
### `vsro128`
|
||
|
||
- **Reads (always):** `VA`, `VB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `VD`
|
||
- **Writes (conditional):** _none_
|
||
|
||
## Status-Register Effects
|
||
|
||
_No condition-register or status-register effects._
|
||
|
||
## Operation (pseudocode)
|
||
|
||
```
|
||
; No hand-written pseudocode for this instruction yet.
|
||
; The authoritative semantics are the Canary emitter snapshot under
|
||
; Implementation References; about half of Canary's emitters open
|
||
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
|
||
; Every side effect is also enumerated in the Register Effects and
|
||
; Status-Register Effects tables above.
|
||
```
|
||
|
||
## C Translation Example
|
||
|
||
```c
|
||
/* No hand-written C yet. Translate the Canary emitter snapshot */
|
||
/* under Implementation References; its HIR maps directly: */
|
||
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
|
||
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
|
||
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
|
||
/* wrap them in f.ByteSwap for the big-endian guest value */
|
||
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
|
||
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
|
||
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
|
||
/* The Register Effects and Status-Register Effects tables above */
|
||
/* enumerate every side effect a faithful translation must emit. */
|
||
```
|
||
|
||
## Implementation References
|
||
|
||
**`vsro`**
|
||
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsro"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
|
||
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1637`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1637)
|
||
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:464`](../../../crates/sylpheed-ppc/src/opcode.rs#L464)
|
||
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:643`](../../../crates/sylpheed-ppc/src/decoder.rs#L643)
|
||
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
|
||
|
||
```cpp
|
||
int InstrEmit_vsro(PPCHIRBuilder& f, const InstrData& i) {
|
||
return InstrEmit_vsro_(f, i.VX.VD, i.VX.VA, i.VX.VB);
|
||
}
|
||
|
||
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1626) ──
|
||
int InstrEmit_vsro_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
|
||
// (VD) <- (VA) >> (VB.b[F] & 0x78) (by octet)
|
||
// TODO(benvanik): flag for shift-by-octet as optimization.
|
||
Value* sh = f.Shr(
|
||
f.And(f.Extract(f.LoadVR(vb), 15, INT8_TYPE), f.LoadConstantInt8(0x78)),
|
||
3);
|
||
Value* v = f.Permute(f.LoadVectorShr(sh), f.LoadZeroVec128(), f.LoadVR(va),
|
||
INT8_TYPE);
|
||
f.StoreVR(vd, v);
|
||
return 0;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
**`vsro128`**
|
||
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsro128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
|
||
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1640`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1640)
|
||
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:465`](../../../crates/sylpheed-ppc/src/opcode.rs#L465)
|
||
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:748`](../../../crates/sylpheed-ppc/src/decoder.rs#L748)
|
||
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
|
||
|
||
```cpp
|
||
int InstrEmit_vsro128(PPCHIRBuilder& f, const InstrData& i) {
|
||
return InstrEmit_vsro_(f, VX128_VD128, VX128_VA128, VX128_VB128);
|
||
}
|
||
|
||
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1626) ──
|
||
int InstrEmit_vsro_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
|
||
// (VD) <- (VA) >> (VB.b[F] & 0x78) (by octet)
|
||
// TODO(benvanik): flag for shift-by-octet as optimization.
|
||
Value* sh = f.Shr(
|
||
f.And(f.Extract(f.LoadVR(vb), 15, INT8_TYPE), f.LoadConstantInt8(0x78)),
|
||
3);
|
||
Value* v = f.Permute(f.LoadVectorShr(sh), f.LoadZeroVec128(), f.LoadVR(va),
|
||
INT8_TYPE);
|
||
f.StoreVR(vd, v);
|
||
return 0;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
<!-- GENERATED: END -->
|
||
|
||
## Special Cases & Edge Conditions
|
||
|
||
- **Whole-register shift-right by octets (bytes).** `VA` is shifted right by `N` bytes, where `N = (VB.b[15] >> 3) & 0xF`. Top end is zero-filled.
|
||
- **Shift count constraint.** Uniform 4-bit count required across `VB`; Canary reads only byte 15.
|
||
- **Pair with [`vsr`](vsr.md) for full bit-level shifts.** `vsro` handles bytes; `vsr` handles the 0..7 residual.
|
||
- **Big-endian.** "Right" = toward LSB end (`VD.b[15]`).
|
||
- **No flags, no VSCR.**
|
||
- **VMX128 sibling `vsro128`.**
|
||
|
||
## Related Instructions
|
||
|
||
- [`vsr`](vsr.md) — bit-level whole-register shift-right.
|
||
- [`vslo`](vslo.md) — shift-left by octet.
|
||
- [`vsldoi`](vsldoi.md) — static-immediate variant.
|
||
- [`vsrb`](vsrb.md), [`vsrh`](vsrh.md), [`vsrw`](vsrw.md) — per-lane logical shifts.
|
||
|
||
## IBM Reference
|
||
|
||
- [AIX 7.3 — `vsro` (Vector Shift Right by Octet)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsro-vector-shift-right-by-octet-instruction)
|
||
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
|