84856fc081
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
4.7 KiB
4.7 KiB
vsubshs — Vector Subtract Signed Half Word Saturate
Category: VMX (Altivec) · Form: VX · Opcode:
0x10000740
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
vsubshs |
vsubshs |
— | Vector Subtract Signed Half Word Saturate |
Syntax
vsubshs [VD], [VA], [VB]
Encoding
vsubshs — form VX
- Opcode word:
0x10000740 - Primary opcode (bits 0–5):
4 - Extended opcode:
1856 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (4) |
| 6–10 | VRT/VD |
destination vector register |
| 11–15 | VRA/VA |
source A vector register |
| 16–20 | VRB/VB |
source B vector register |
| 21–31 | XO |
extended opcode (11 bits) |
Operands
| Field | Role | Description |
|---|---|---|
VA |
vsubshs: read | Source A vector register. |
VB |
vsubshs: read | Source B vector register. |
VD |
vsubshs: write | Destination vector register. |
VSCR |
vsubshs: write | Vector Status and Control Register (NJ/SAT bits). |
Register Effects
vsubshs
- Reads (always):
VA,VB - Reads (conditional): none
- Writes (always):
VD,VSCR - Writes (conditional): none
Status-Register Effects
vsubshs: VSCR[SAT] may be stickied on saturating vector operations.
Operation (pseudocode)
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
C Translation Example
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
vsubshs
- Canary XML:
tools/ppc-instructions.xml— search formnem="vsubshs" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:1688 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:472 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:663
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_vsubshs(PPCHIRBuilder& f, const InstrData& i) {
// (VD) <- clamp(EXTS(VA) + ¬EXTS(VB) + 1, -2^15, 2^15-1)
Value* v = f.VectorSub(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT16_TYPE,
ARITHMETIC_SATURATE);
f.StoreSAT(f.DidSaturate(v));
f.StoreVR(i.VX.VD, v);
return 0;
}
Special Cases & Edge Conditions
- Signed half-word saturating subtract.
VD.h[i] = clamp_int16(VA.h[i] − VB.h[i])for 8 lanes. Overflow clamps to±0x7FFFand sticky-setsVSCR[SAT]. Canary clamps the lanes (VectorSubwithARITHMETIC_SATURATE) but never recordsSAT(x64DID_SATURATEis a stub). - Sticky VSCR[SAT].
- Big-endian half-word lanes.
- No
Rc, no XER. - No VMX128 sibling.
Related Instructions
vaddshs— signed half-word saturating add.vsubuhs,vsubuhm— unsigned half-word sub (sat / mod).vsubsbs,vsubsws— signed saturating subs at byte / word width.