[Testing] add more arithmetic instruction tests

src/xenia/cpu/ppc/testing/instr_vaddcuw.s

@@ -0,0 +1,44 @@
+test_vaddcuw_1:
+  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vaddcuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vaddcuw_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, 80000000, 7FFFFFFF]
+  #_ REGISTER_IN v4 [00000001, 00000000, 80000000, 00000001]
+  vaddcuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, 80000000, 7FFFFFFF]
+  #_ REGISTER_OUT v4 [00000001, 00000000, 80000000, 00000001]
+  #_ REGISTER_OUT v5 [00000001, 00000000, 00000001, 00000000]
+
+test_vaddcuw_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vaddcuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
+
+test_vaddcuw_4:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vaddcuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vaddcuw_5:
+  #_ REGISTER_IN v3 [FFFFFFFE, 7FFFFFFF, 80000000, 12345678]
+  #_ REGISTER_IN v4 [00000001, 80000000, 7FFFFFFF, EDCBA987]
+  vaddcuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFE, 7FFFFFFF, 80000000, 12345678]
+  #_ REGISTER_OUT v4 [00000001, 80000000, 7FFFFFFF, EDCBA987]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]

src/xenia/cpu/ppc/testing/instr_vaddubm.s

@@ -0,0 +1,44 @@
+test_vaddubm_1:
+  #_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vaddubm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [02020202, 02020202, 02020202, 02020202]
+
+test_vaddubm_2:
+  #_ REGISTER_IN v3 [FF80017F, FE81027E, FD82037D, FC83047C]
+  #_ REGISTER_IN v4 [01020304, 02030405, 03040506, 04050607]
+  vaddubm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FF80017F, FE81027E, FD82037D, FC83047C]
+  #_ REGISTER_OUT v4 [01020304, 02030405, 03040506, 04050607]
+  #_ REGISTER_OUT v5 [00820483, 00840683, 00860883, 00880A83]
+
+test_vaddubm_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vaddubm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vaddubm_4:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vaddubm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vaddubm_5:
+  #_ REGISTER_IN v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vaddubm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]

src/xenia/cpu/ppc/testing/instr_vadduwm.s

@@ -0,0 +1,44 @@
+test_vadduwm_1:
+  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vadduwm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000002, 00000002, 00000002, 00000002]
+
+test_vadduwm_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, 80000000, 7FFFFFFF, 12345678]
+  #_ REGISTER_IN v4 [00000001, 80000001, 00000001, EDCBA988]
+  vadduwm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, 80000000, 7FFFFFFF, 12345678]
+  #_ REGISTER_OUT v4 [00000001, 80000001, 00000001, EDCBA988]
+  #_ REGISTER_OUT v5 [00000000, 00000001, 80000000, 00000000]
+
+test_vadduwm_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vadduwm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
+
+test_vadduwm_4:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vadduwm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vadduwm_5:
+  #_ REGISTER_IN v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vadduwm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]

src/xenia/cpu/ppc/testing/instr_vsubcuw.s

@@ -0,0 +1,44 @@
+test_vsubcuw_1:
+  #_ REGISTER_IN v3 [00000002, 00000002, 00000002, 00000002]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsubcuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
+
+test_vsubcuw_2:
+  #_ REGISTER_IN v3 [00000001, 00000000, 80000000, 7FFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000001, 7FFFFFFF, 80000000]
+  vsubcuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000000, 80000000, 7FFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000001, 7FFFFFFF, 80000000]
+  #_ REGISTER_OUT v5 [00000001, 00000000, 00000001, 00000000]
+
+test_vsubcuw_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsubcuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
+
+test_vsubcuw_4:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsubcuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
+
+test_vsubcuw_5:
+  #_ REGISTER_IN v3 [00000000, 7FFFFFFF, 80000000, 12345678]
+  #_ REGISTER_IN v4 [00000001, 80000000, 7FFFFFFF, EDCBA987]
+  vsubcuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 7FFFFFFF, 80000000, 12345678]
+  #_ REGISTER_OUT v4 [00000001, 80000000, 7FFFFFFF, EDCBA987]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000001, 00000000]

src/xenia/cpu/ppc/testing/instr_vsububm.s

@@ -0,0 +1,44 @@
+test_vsububm_1:
+  #_ REGISTER_IN v3 [02020202, 02020202, 02020202, 02020202]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsububm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
+
+test_vsububm_2:
+  #_ REGISTER_IN v3 [0080017F, FE81027E, FD82037D, FC83047C]
+  #_ REGISTER_IN v4 [01810280, 02820380, 03830480, 04840580]
+  vsububm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [0080017F, FE81027E, FD82037D, FC83047C]
+  #_ REGISTER_OUT v4 [01810280, 02820380, 03830480, 04840580]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FCFFFFFE, FAFFFFFD, F8FFFFFC]
+
+test_vsububm_3:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsububm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vsububm_4:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsububm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsububm_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vsububm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]

src/xenia/cpu/ppc/testing/instr_vsubuwm.s

@@ -0,0 +1,44 @@
+test_vsubuwm_1:
+  #_ REGISTER_IN v3 [00000002, 00000002, 00000002, 00000002]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsubuwm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
+
+test_vsubuwm_2:
+  #_ REGISTER_IN v3 [00000000, 80000000, 7FFFFFFF, 00000001]
+  #_ REGISTER_IN v4 [00000001, 80000001, 80000000, 00000002]
+  vsubuwm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 80000000, 7FFFFFFF, 00000001]
+  #_ REGISTER_OUT v4 [00000001, 80000001, 80000000, 00000002]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vsubuwm_3:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsubuwm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vsubuwm_4:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vsubuwm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vsubuwm_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vsubuwm v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]