Directly check PEB for IsDebuggerAttached
Add constexpr getters to magicdiv class so it can be used from jitted x64/dxbc Track the guest return address as well for guest/host sync, if multiple entries have the same guest stack find the first one with a matching guest retaddr. this fixes epic mickey 2 (which the previous guest-stack change had allowed to go ingame for a bit) and potentially also a crash in fable3. Break if under debugger when stackpoints are overflowed Add much more useful output for host exceptions, print out xenia_canary.exe relative offsets if exception is in module, formatmessage for ntstatus/win32err, strerror Minor d3d12 microoptimization, instead of doing SetEventOnCompletion + WaitForSingleObject do SetEventOnCompletion w/ nullptr so that the wait happens in kernel mode, avoiding two extra context switches add unimplemented kernel functions: ExAllocatePoolWithTag ObReferenceObject ObDereferenceObject has no return value. Log a message when ObDereferenceObject/Reference receive unregistered guest kernel objects gave ObLookupThreadByThreadId its correct error status hoist object_types initialization out of ObReferenceObjectByHandle Fix out parameter values on error for a few kernel funcs add note about msr to KeSetCurrentStackPointers add X_STATUS_OBJECT_TYPE_MISMATCH check for xeNtSetEvent add msr_mask field to X_KPCR
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@@ -3124,7 +3124,6 @@ bool D3D12CommandProcessor::IssueCopy_ReadbackResolvePath() {
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auto physaddr = memory_->TranslatePhysical(written_address);
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memory::vastcpy(physaddr, (uint8_t*)readback_mapping,
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written_length);
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// XEDmaCpy(physaddr, readback_mapping, written_length);
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D3D12_RANGE readback_write_range = {};
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readback_buffer->Unmap(0, &readback_write_range);
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}
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@@ -3152,9 +3151,7 @@ void D3D12CommandProcessor::CheckSubmissionFence(uint64_t await_submission) {
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direct_queue->Signal(queue_operations_since_submission_fence_,
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fence_value) &&
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SUCCEEDED(queue_operations_since_submission_fence_
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->SetEventOnCompletion(fence_value,
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fence_completion_event_)))) {
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WaitForSingleObject(fence_completion_event_, INFINITE);
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->SetEventOnCompletion(fence_value, nullptr)))) {
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queue_operations_done_since_submission_signal_ = false;
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} else {
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XELOGE(
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@@ -3170,9 +3167,8 @@ void D3D12CommandProcessor::CheckSubmissionFence(uint64_t await_submission) {
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uint64_t submission_completed_before = submission_completed_;
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submission_completed_ = submission_fence_->GetCompletedValue();
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if (submission_completed_ < await_submission) {
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if (SUCCEEDED(submission_fence_->SetEventOnCompletion(
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await_submission, fence_completion_event_))) {
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WaitForSingleObject(fence_completion_event_, INFINITE);
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if (SUCCEEDED(submission_fence_->SetEventOnCompletion(await_submission,
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nullptr))) {
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submission_completed_ = submission_fence_->GetCompletedValue();
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}
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}
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@@ -43,6 +43,7 @@ DEFINE_bool(
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"Allow stencil reference output usage on Direct3D 12 on Intel GPUs - not "
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"working on UHD Graphics 630 as of March 2021 (driver 27.20.0100.8336).",
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"GPU");
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DEFINE_bool(no_discard_stencil_in_transfer_pipelines, false, "bleh", "GPU");
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// TODO(Triang3l): Make ROV the default when it's optimized better (for
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// instance, using static shader modifications to pass render target
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// parameters).
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@@ -2940,7 +2941,7 @@ D3D12RenderTargetCache::GetOrCreateTransferPipelines(TransferShaderKey key) {
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// r0.xy = destination pixel XY index within the 32bpp tile
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// r0.zw = 32bpp tile XY index
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a.OpUDiv(dxbc::Dest::R(0, 0b1100), dxbc::Dest::R(0, 0b0011),
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dxbc::Src::R(0, 0b01000100),
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dxbc::Src::R(0, dxbc::Src::kXYXY),
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dxbc::Src::LU(dest_tile_width_pixels, dest_tile_height_pixels,
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dest_tile_width_pixels, dest_tile_height_pixels));
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@@ -4189,12 +4190,14 @@ D3D12RenderTargetCache::GetOrCreateTransferPipelines(TransferShaderKey key) {
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break;
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case TransferOutput::kStencilBit:
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// Discard the sample if the needed stencil bit is not set.
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assert_true(cbuffer_index_stencil_mask != UINT32_MAX);
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a.OpAnd(dxbc::Dest::R(0, 0b0001), dxbc::Src::R(1, dxbc::Src::kXXXX),
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dxbc::Src::CB(cbuffer_index_stencil_mask,
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kTransferCBVRegisterStencilMask, 0,
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dxbc::Src::kXXXX));
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a.OpDiscard(false, dxbc::Src::R(0, dxbc::Src::kXXXX));
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if (!cvars::no_discard_stencil_in_transfer_pipelines) {
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assert_true(cbuffer_index_stencil_mask != UINT32_MAX);
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a.OpAnd(dxbc::Dest::R(0, 0b0001), dxbc::Src::R(1, dxbc::Src::kXXXX),
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dxbc::Src::CB(cbuffer_index_stencil_mask,
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kTransferCBVRegisterStencilMask, 0,
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dxbc::Src::kXXXX));
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a.OpDiscard(false, dxbc::Src::R(0, dxbc::Src::kXXXX));
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}
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break;
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}
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}
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@@ -1046,6 +1046,7 @@ struct Src : OperandAddress {
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kYYYY = 0b01010101,
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kZZZZ = 0b10101010,
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kWWWW = 0b11111111,
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kXYXY = 0b01000100
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};
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// Ignored for 0-component and 1-component operand types.
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