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[GPU] Remove most hardcoded register/instruction layouts from common and D3D12 code

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This commit is contained in:
Triang3l
2019-10-20 19:40:37 +03:00
parent f83269cf8c
commit a9ed73bdd1
24 changed files with 896 additions and 942 deletions
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5
src/xenia/gpu/vulkan/buffer_cache.cc
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@@ -654,9 +654,8 @@ VkDescriptorSet BufferCache::PrepareVertexSet(
// trace_writer_.WriteMemoryRead(physical_address, source_length);
// Upload (or get a cached copy of) the buffer.
auto buffer_ref =
UploadVertexBuffer(command_buffer, physical_address, source_length,
static_cast<Endian>(fetch->endian), fence);
auto buffer_ref = UploadVertexBuffer(command_buffer, physical_address,
source_length, fetch->endian, fence);
if (buffer_ref.second == VK_WHOLE_SIZE) {
// Failed to upload buffer.
XELOGW("Failed to upload vertex buffer!");

16
src/xenia/gpu/vulkan/pipeline_cache.cc
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@@ -815,13 +815,13 @@ bool PipelineCache::SetDynamicState(VkCommandBuffer command_buffer,
push_constants_dirty |=
SetShadowRegister(&regs.rb_colorcontrol, XE_GPU_REG_RB_COLORCONTROL);
push_constants_dirty |=
SetShadowRegister(&regs.rb_color_info, XE_GPU_REG_RB_COLOR_INFO);
SetShadowRegister(&regs.rb_color_info.value, XE_GPU_REG_RB_COLOR_INFO);
push_constants_dirty |=
SetShadowRegister(&regs.rb_color1_info, XE_GPU_REG_RB_COLOR1_INFO);
SetShadowRegister(&regs.rb_color1_info.value, XE_GPU_REG_RB_COLOR1_INFO);
push_constants_dirty |=
SetShadowRegister(&regs.rb_color2_info, XE_GPU_REG_RB_COLOR2_INFO);
SetShadowRegister(&regs.rb_color2_info.value, XE_GPU_REG_RB_COLOR2_INFO);
push_constants_dirty |=
SetShadowRegister(&regs.rb_color3_info, XE_GPU_REG_RB_COLOR3_INFO);
SetShadowRegister(&regs.rb_color3_info.value, XE_GPU_REG_RB_COLOR3_INFO);
push_constants_dirty |=
SetShadowRegister(&regs.rb_alpha_ref, XE_GPU_REG_RB_ALPHA_REF);
push_constants_dirty |=
@@ -1503,13 +1503,13 @@ PipelineCache::UpdateStatus PipelineCache::UpdateColorBlendState() {
bool dirty = false;
dirty |= SetShadowRegister(&regs.rb_color_mask, XE_GPU_REG_RB_COLOR_MASK);
dirty |=
SetShadowRegister(&regs.rb_blendcontrol[0], XE_GPU_REG_RB_BLENDCONTROL_0);
SetShadowRegister(&regs.rb_blendcontrol[0], XE_GPU_REG_RB_BLENDCONTROL0);
dirty |=
SetShadowRegister(&regs.rb_blendcontrol[1], XE_GPU_REG_RB_BLENDCONTROL_1);
SetShadowRegister(&regs.rb_blendcontrol[1], XE_GPU_REG_RB_BLENDCONTROL1);
dirty |=
SetShadowRegister(&regs.rb_blendcontrol[2], XE_GPU_REG_RB_BLENDCONTROL_2);
SetShadowRegister(&regs.rb_blendcontrol[2], XE_GPU_REG_RB_BLENDCONTROL2);
dirty |=
SetShadowRegister(&regs.rb_blendcontrol[3], XE_GPU_REG_RB_BLENDCONTROL_3);
SetShadowRegister(&regs.rb_blendcontrol[3], XE_GPU_REG_RB_BLENDCONTROL3);
dirty |= SetShadowRegister(&regs.rb_modecontrol, XE_GPU_REG_RB_MODECONTROL);
XXH64_update(&hash_state_, &regs, sizeof(regs));
if (!dirty) {

8
src/xenia/gpu/vulkan/pipeline_cache.h
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@@ -292,10 +292,10 @@ class PipelineCache {
reg::SQ_PROGRAM_CNTL sq_program_cntl;
uint32_t sq_context_misc;
uint32_t rb_colorcontrol;
uint32_t rb_color_info;
uint32_t rb_color1_info;
uint32_t rb_color2_info;
uint32_t rb_color3_info;
reg::RB_COLOR_INFO rb_color_info;
reg::RB_COLOR_INFO rb_color1_info;
reg::RB_COLOR_INFO rb_color2_info;
reg::RB_COLOR_INFO rb_color3_info;
float rb_alpha_ref;
uint32_t pa_su_point_size;

16
src/xenia/gpu/vulkan/vulkan_command_processor.cc
View File

@@ -962,7 +962,7 @@ bool VulkanCommandProcessor::IssueCopy() {
break;
}
assert_true(fetch->type == 3);
assert_true(fetch->endian == 2);
assert_true(fetch->endian == Endian::k8in32);
assert_true(fetch->size == 6);
const uint8_t* vertex_addr = memory_->TranslatePhysical(fetch->address << 2);
trace_writer_.WriteMemoryRead(fetch->address << 2, fetch->size * 4);
@@ -974,7 +974,7 @@ bool VulkanCommandProcessor::IssueCopy() {
float dest_points[6];
for (int i = 0; i < 6; i++) {
dest_points[i] =
GpuSwap(xe::load<float>(vertex_addr + i * 4), Endian(fetch->endian)) +
GpuSwap(xe::load<float>(vertex_addr + i * 4), fetch->endian) +
vtx_offset;
}
@@ -1000,10 +1000,10 @@ bool VulkanCommandProcessor::IssueCopy() {
if (is_color_source) {
// Source from a color target.
reg::RB_COLOR_INFO color_info[4] = {
regs[XE_GPU_REG_RB_COLOR_INFO].u32,
regs[XE_GPU_REG_RB_COLOR1_INFO].u32,
regs[XE_GPU_REG_RB_COLOR2_INFO].u32,
regs[XE_GPU_REG_RB_COLOR3_INFO].u32,
regs.Get<reg::RB_COLOR_INFO>(),
regs.Get<reg::RB_COLOR_INFO>(XE_GPU_REG_RB_COLOR1_INFO),
regs.Get<reg::RB_COLOR_INFO>(XE_GPU_REG_RB_COLOR2_INFO),
regs.Get<reg::RB_COLOR_INFO>(XE_GPU_REG_RB_COLOR3_INFO),
};
color_edram_base = color_info[copy_src_select].color_base;
color_format = color_info[copy_src_select].color_format;
@@ -1023,7 +1023,7 @@ bool VulkanCommandProcessor::IssueCopy() {
Endian resolve_endian = Endian::k8in32;
if (copy_regs->copy_dest_info.copy_dest_endian <= Endian128::k16in32) {
resolve_endian =
static_cast<Endian>(copy_regs->copy_dest_info.copy_dest_endian.value());
static_cast<Endian>(copy_regs->copy_dest_info.copy_dest_endian);
}
// Demand a resolve texture from the texture cache.
@@ -1289,7 +1289,7 @@ bool VulkanCommandProcessor::IssueCopy() {
// Perform any requested clears.
uint32_t copy_depth_clear = regs[XE_GPU_REG_RB_DEPTH_CLEAR].u32;
uint32_t copy_color_clear = regs[XE_GPU_REG_RB_COLOR_CLEAR].u32;
uint32_t copy_color_clear_low = regs[XE_GPU_REG_RB_COLOR_CLEAR_LOW].u32;
uint32_t copy_color_clear_low = regs[XE_GPU_REG_RB_COLOR_CLEAR_LO].u32;
assert_true(copy_color_clear == copy_color_clear_low);
if (color_clear_enabled) {