[Vulkan] add no_discard_stencil_in_transfer_pipelines support
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@@ -37,7 +37,6 @@ DEFINE_bool(
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"Allow stencil reference output usage on Direct3D 12 on Intel GPUs - not "
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"Allow stencil reference output usage on Direct3D 12 on Intel GPUs - not "
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"working on UHD Graphics 630 as of March 2021 (driver 27.20.0100.8336).",
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"working on UHD Graphics 630 as of March 2021 (driver 27.20.0100.8336).",
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"GPU");
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"GPU");
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DEFINE_bool(no_discard_stencil_in_transfer_pipelines, false, "bleh", "GPU");
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// TODO(Triang3l): Make ROV the default when it's optimized better (for
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// TODO(Triang3l): Make ROV the default when it's optimized better (for
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// instance, using static shader modifications to pass render target
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// instance, using static shader modifications to pass render target
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// parameters).
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// parameters).
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@@ -84,3 +84,8 @@ DEFINE_int32(anisotropic_override, -1,
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" 4 = Force 8x anisotropic filtering\n"
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" 4 = Force 8x anisotropic filtering\n"
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" 5 = Force 16x anisotropic filtering",
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" 5 = Force 16x anisotropic filtering",
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"GPU");
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"GPU");
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DEFINE_bool(no_discard_stencil_in_transfer_pipelines, false,
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"Skip stencil bit discard in render target transfer pipelines. "
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"May improve performance on some GPUs.",
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"GPU");
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@@ -34,6 +34,8 @@ DECLARE_int32(anisotropic_override);
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DECLARE_bool(disassemble_pm4);
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DECLARE_bool(disassemble_pm4);
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DECLARE_bool(no_discard_stencil_in_transfer_pipelines);
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#define XE_GPU_FINE_GRAINED_DRAW_SCOPES 1
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#define XE_GPU_FINE_GRAINED_DRAW_SCOPES 1
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#endif // XENIA_GPU_GPU_FLAGS_H_
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#endif // XENIA_GPU_GPU_FLAGS_H_
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@@ -19,6 +19,7 @@
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#include "xenia/base/logging.h"
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#include "xenia/base/logging.h"
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#include "xenia/base/math.h"
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#include "xenia/base/math.h"
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#include "xenia/gpu/draw_util.h"
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#include "xenia/gpu/draw_util.h"
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#include "xenia/gpu/gpu_flags.h"
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#include "xenia/gpu/registers.h"
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#include "xenia/gpu/registers.h"
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#include "xenia/gpu/spirv_builder.h"
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#include "xenia/gpu/spirv_builder.h"
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#include "xenia/gpu/spirv_compatibility.h"
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#include "xenia/gpu/spirv_compatibility.h"
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@@ -4281,7 +4282,7 @@ VkShaderModule VulkanRenderTargetCache::GetTransferShader(
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}
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}
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} break;
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} break;
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case TransferOutput::kStencilBit: {
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case TransferOutput::kStencilBit: {
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if (packed) {
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if (packed && !cvars::no_discard_stencil_in_transfer_pipelines) {
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// Kill the sample if the needed stencil bit is not set.
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// Kill the sample if the needed stencil bit is not set.
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assert_true(push_constants_member_stencil_mask != UINT32_MAX);
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assert_true(push_constants_member_stencil_mask != UINT32_MAX);
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id_vector_temp.clear();
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id_vector_temp.clear();
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