Fixed a bug with readback_resolve and readback_memexport that was responsible for a large portion of their overhead. readback_memexport and resolve are now usable for games, depending on your hardware. in my case games that were slideshows now run at like 20-30 fps, and my hardware isnt the best for xenia.
add split_map class for mapping keys to values in a way that optimizes for frequent searches and infrequent insertions/removals remove jump table implementation of GetColorRenderTargetFormatComponentCount, it was appearing relatively high in profiles. instead pack the component counts into a single 32 bit word, which is indexed by shifting Add cvar to align all basic blocks to a boundary Add mmio aware load paths liberally apply XE_RESTRICT in ringbuffer related code Removed the IS_TRUE and IS_FALSE opcodes, they were pointless duplicates of COMPARE_EQ/COMPARE_NE and i want to simplify our set of opcodes for future backends More work on LVSR/LVSL/STVR/STVL opcodes Optimized X64 translated code emission, now only compute instrkey once Add code for pre-computing integer division magic numbers Optimized GetHostViewportInfo a little Move args for GetHostViewportInfo into a class, cache the result and compare for future queries. moved GetHostViewportInfo far lower on the profile Add (currently not functional, and very racy) asynchronous memcpy code. will improve it and actually use it in future commits. Add non-temporal memcpy function for huge page-aligned allocations. Used for copying to shared memory/readback hoist are_accumulated_render_targets_valid_ check out of loop in render_target_cache already bound check. Add stosb/movsb code for small constant memcpys/memsets that arent worth the overhead of memcpy/memset
This commit is contained in:
chss95cs@gmail.com
@@ -377,29 +377,45 @@ int64_t m128_i64(const __m128& v) {
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return m128_i64<N>(_mm_castps_pd(v));
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}
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/*
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std::min/max float has handling for nans, where if either argument is nan the first argument is returned
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minss/maxss are different, if either argument is nan the second operand to the instruction is returned
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this is problematic because we have no assurances from the compiler on the argument ordering
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std::min/max float has handling for nans, where if either argument is
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nan the first argument is returned
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so only use in places where nan handling is not needed
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minss/maxss are different, if either argument is nan the second operand
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to the instruction is returned this is problematic because we have no
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assurances from the compiler on the argument ordering
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so only use in places where nan handling is not needed
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*/
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static float xe_minf(float x, float y) {
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XE_FORCEINLINE
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static float ArchMin(float x, float y) {
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return _mm_cvtss_f32(_mm_min_ss(_mm_set_ss(x), _mm_set_ss(y)));
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}
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static float xe_maxf(float x, float y) {
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XE_FORCEINLINE
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static float ArchMax(float x, float y) {
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return _mm_cvtss_f32(_mm_max_ss(_mm_set_ss(x), _mm_set_ss(y)));
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}
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static float xe_rcpf(float den) {
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XE_FORCEINLINE
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static float ArchReciprocal(float den) {
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return _mm_cvtss_f32(_mm_rcp_ss(_mm_set_ss(den)));
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}
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#else
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static float xe_minf(float x, float y) { return std::min<float>(x, y); }
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static float xe_maxf(float x, float y) { return std::max<float>(x, y); }
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static float xe_rcpf(float den) { return 1.0f / den; }
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static float ArchMin(float x, float y) { return std::min<float>(x, y); }
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static float ArchMax(float x, float y) { return std::max<float>(x, y); }
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static float ArchReciprocal(float den) { return 1.0f / den; }
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#endif
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XE_FORCEINLINE
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static float RefineReciprocal(float initial, float den) {
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float t0 = initial * den;
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float t1 = t0 * initial;
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float rcp2 = initial + initial;
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return rcp2 - t1;
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}
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XE_FORCEINLINE
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static float ArchReciprocalRefined(float den) {
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return RefineReciprocal(ArchReciprocal(den), den);
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}
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// Similar to the C++ implementation of XMConvertFloatToHalf and
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// XMConvertHalfToFloat from DirectXMath 3.00 (pre-3.04, which switched from the
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@@ -494,7 +510,101 @@ inline T sat_sub(T a, T b) {
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}
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return T(result);
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}
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namespace divisors {
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union IDivExtraInfo {
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uint32_t value_;
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struct {
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uint32_t shift_ : 31;
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uint32_t add_ : 1;
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} info;
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};
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// returns magicnum multiplier
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static uint32_t PregenerateUint32Div(uint32_t _denom, uint32_t& out_extra) {
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IDivExtraInfo extra;
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uint32_t d = _denom;
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int p;
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uint32_t nc, delta, q1, r1, q2, r2;
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struct {
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unsigned M;
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int a;
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int s;
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} magu;
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magu.a = 0;
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nc = -1 - ((uint32_t) - (int32_t)d) % d;
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p = 31;
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q1 = 0x80000000 / nc;
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r1 = 0x80000000 - q1 * nc;
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q2 = 0x7FFFFFFF / d;
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r2 = 0x7FFFFFFF - q2 * d;
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do {
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p += 1;
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if (r1 >= nc - r1) {
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q1 = 2 * q1 + 1;
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r1 = 2 * r1 - nc;
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} else {
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q1 = 2 * q1;
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r1 = 2 * r1;
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}
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if (r2 + 1 >= d - r2) {
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if (q2 >= 0x7FFFFFFF) {
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magu.a = 1;
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}
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q2 = 2 * q2 + 1;
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r2 = 2 * r2 + 1 - d;
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} else {
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if (q2 >= 0x80000000U) {
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magu.a = 1;
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}
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q2 = 2 * q2;
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r2 = 2 * r2 + 1;
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}
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delta = d - 1 - r2;
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} while (p < 64 && (q1 < delta || r1 == 0));
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extra.info.add_ = magu.a;
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extra.info.shift_ = p - 32;
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out_extra = extra.value_;
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return static_cast<uint64_t>(q2 + 1);
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}
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static inline uint32_t ApplyUint32Div(uint32_t num, uint32_t mul,
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uint32_t extradata) {
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IDivExtraInfo extra;
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extra.value_ = extradata;
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uint32_t result = ((uint64_t)(num) * (uint64_t)mul) >> 32;
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if (extra.info.add_) {
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uint32_t addend = result + num;
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addend = ((addend < result ? 0x80000000 : 0) | addend);
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result = addend;
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}
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return result >> extra.info.shift_;
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}
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static inline uint32_t ApplyUint32UMod(uint32_t num, uint32_t mul,
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uint32_t extradata, uint32_t original) {
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uint32_t dived = ApplyUint32Div(num, mul, extradata);
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unsigned result = num - (dived * original);
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return result;
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}
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struct MagicDiv {
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uint32_t multiplier_;
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uint32_t extradata_;
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MagicDiv() : multiplier_(0), extradata_(0) {}
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MagicDiv(uint32_t original) {
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multiplier_ = PregenerateUint32Div(original, extradata_);
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}
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uint32_t Apply(uint32_t numerator) const {
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return ApplyUint32Div(numerator, multiplier_, extradata_);
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}
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};
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} // namespace divisors
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} // namespace xe
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#endif // XENIA_BASE_MATH_H_
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