[CPU/PPC] Implement and fix FPSCR-related instructions
mcrfs: Implement Move CR from FPSCR instruction Copies a 4-bit FPSCR field to CR and clears the FPSCR exception bits. mffsx: Fix Rc bit handling Properly update CR1 from FPSCR when Rc=1 instead of returning error. Previously treated Rc=1 as unimplemented. fcfidx: Fix Rc field access Use i.X.Rc instead of i.A.Rc for correct instruction format. fcfid uses X format, not A format.
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@@ -237,7 +237,7 @@ int InstrEmit_fcfidx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- signed_int64_to_double( frB )
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Value* v = f.Convert(f.Cast(f.LoadFPR(i.X.RB), INT64_TYPE), FLOAT64_TYPE);
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f.StoreFPR(i.X.RT, v);
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f.UpdateFPSCR(v, i.A.Rc);
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f.UpdateFPSCR(v, i.X.Rc);
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return 0;
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}
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@@ -352,17 +352,37 @@ int InstrEmit_fcmpu(PPCHIRBuilder& f, const InstrData& i) {
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// Floating-point status and control register (A
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int InstrEmit_mcrfs(PPCHIRBuilder& f, const InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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// mcrfs CRFD, CRFS
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// CR[4*CRFD:4*CRFD+3] <- FPSCR[4*CRFS:4*CRFS+3]
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// FPSCR[4*CRFS:4*CRFS+3] <- 0 (exception bits cleared)
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uint32_t crfd = i.X.RT >> 2; // Destination CR field
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uint32_t crfs = i.X.RA >> 2; // Source FPSCR field
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Value* fpscr = f.LoadFPSCR();
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// Extract 4-bit field from FPSCR
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// FPSCR fields are numbered from left to right (0-7), with field 0 being bits
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// 0-3
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uint32_t shift = 4 * (7 - crfs);
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Value* fpscr_field = f.And(f.Shr(fpscr, shift), f.LoadConstantUint32(0xF));
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// Store to CR field (need to shift to proper position in 64-bit CR)
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f.StoreCR(crfd, f.Shl(f.ZeroExtend(fpscr_field, INT64_TYPE), 4 * (7 - crfd)));
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// Clear the FPSCR field (set to 0)
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uint32_t mask = ~(0xF << shift);
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f.StoreFPSCR(f.And(fpscr, f.LoadConstantUint32(mask)));
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return 0;
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}
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int InstrEmit_mffsx(PPCHIRBuilder& f, const InstrData& i) {
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if (i.X.Rc) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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Value* v = f.Cast(f.ZeroExtend(f.LoadFPSCR(), INT64_TYPE), FLOAT64_TYPE);
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f.StoreFPR(i.X.RT, v);
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if (i.X.Rc) {
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f.CopyFPSCRToCR1();
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}
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return 0;
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}
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