Commit Graph

20 Commits

Author SHA1 Message Date
Gliniak
674870d881 [D3D12] Fixed stability issues (Graphics lost) on AMD GPUs
- This includes infamous 6000 series crashes and crashes on newer drivers for 7000 and 9000 series

Issue was caused by returning invalid (negative) address from MaxAs opcode.

Currently it is unknown if this behaviour is correct and should be checked on console, so slight graphical issues might be present
2025-04-28 23:34:17 +02:00
Triang3l
53f98d1fe6 [GPU/D3D12] Memexport from anywhere in control flow + 8/16bpp memexport
There's no limit on the number of memory exports in a shader on the real
Xenos, and exports can be done anywhere, including in loops. Now, instead
of deferring the exports to the end of the shader, and assuming that export
allocs are executed only once, Xenia flushes exports when it reaches an
alloc (allocs terminate memory exports on Xenos, as well as individual ALU
instructions with `serialize`, but not handling this case for simplicity,
it's only truly mandatory to flush memory exports before starting a new
one), the end of the shader, or a pixel with outstanding exports is killed.

To know which eM# registers need to be flushed to the memory, traversing
the successors of each exec potentially writing any eM#, and specifying
that certain eM# registers might have potentially been written before each
reached control flow instruction, until a flush point or the end of the
shader is reached.

Also, some games export to sub-32bpp formats. These are now supported via
atomic AND clearing the bits of the dword to replace followed by an atomic
OR inserting the new byte/short.
2023-05-05 21:32:02 +03:00
Triang3l
75d805245d [DXBC] discard pixels from kill with ROV instead of returning
Keep the current lane active as it may be needed for derivatives.
2023-04-09 20:13:22 +03:00
Triang3l
b42680abf7 [GPU] Shader ALU refactoring + documentation
Mainly move instruction info from the ShaderTranslator to xe::gpu::ucode for future use in the CPU shader interpreter
2022-04-27 20:52:20 +03:00
Triang3l
9a74df491f [DXBC] dxbc.h with non-translator-specific parts 2021-01-04 16:15:50 +03:00
Triang3l
ae3b68c7b6 [DXBC] Fast mul path only for fully identical components because neg is post-abs 2020-10-30 22:31:30 +03:00
Triang3l
feb8258a5e [DXBC] Multiplication signed zero handling 2020-10-30 22:14:38 +03:00
Triang3l
814990f686 [DXBC] ALU scalar ops to new codegen 2020-05-10 20:57:33 +03:00
Triang3l
ef37cbb955 [DXBC] Fix an outdated comment about cube operands 2020-05-10 16:35:40 +03:00
Triang3l
b79ba69548 [DXBC] ALU vector ops to new codegen 2020-05-10 16:33:39 +03:00
Triang3l
3aa0ce3096 [GPU] Shader translator refactoring (mostly ALU), fixes for disassembly round trip and write masks 2020-05-08 23:57:51 +03:00
Triang3l
1799585e92 [DXBC] Control flow to new DXBC code 2020-04-25 19:30:01 +03:00
Triang3l
d18e63e6e2 [D3D12] Always write original shader source in DXBC if PIX is attached 2020-02-16 18:09:22 +03:00
Triang3l
352f12f92e [D3D12] Switch from gflags to cvars 2019-08-03 16:53:23 +03:00
Triang3l
6672997108 [D3D12] ROV early Z and full rewrite, shader scalar optimizations 2019-07-11 09:31:58 +03:00
Triang3l
66a9c9d812 [GPU] Store ALU result after both vector and scalar instructions 2019-04-20 20:30:01 +03:00
Triang3l
e5bcedfd1f [D3D12] DXBC: Fix 0*anything check in muls_prev 2019-01-12 13:07:45 +03:00
Triang3l
bd9aae016f [D3D12] DXBC: eA and eM registers 2018-12-22 19:51:12 +03:00
Triang3l
645f450321 [D3D12] DXBC: Fix UAV and sampler operands 2018-12-22 14:26:18 +03:00
Triang3l
cbba86fcf0 [D3D12] Split DXBC shader translator into multiple files 2018-12-19 14:24:16 +03:00