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5860a8fdc6201063c7e4f87c3acc5ca3626d69bf
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1482 Commits

Author SHA1 Message Date
Triang3l
5860a8fdc6 [D3D12] DXBC: Add a missing STAT increment to memexport 2018-12-28 08:13:35 +03:00
Triang3l
ed09cac440 [D3D12] DXBC: vfetch RoundIndex, vertex index signedness fixes 2018-12-28 08:11:34 +03:00
Triang3l
ec7667ce1b [D3D12] Broken memexport shader code 2018-12-27 20:43:17 +03:00
Triang3l
bd9aae016f [D3D12] DXBC: eA and eM registers 2018-12-22 19:51:12 +03:00
Triang3l
e803ee84d5 [D3D12] Bind shared memory as UAV with memexport 2018-12-22 15:39:47 +03:00
Triang3l
645f450321 [D3D12] DXBC: Fix UAV and sampler operands 2018-12-22 14:26:18 +03:00
Triang3l
6025599d3b [D3D12] Request memory for memexport in shared memory 2018-12-22 00:57:31 +03:00
Triang3l
0aeff797e5 [D3D12] DXBC: Allocate multiple registers with PushSystemTemp 2018-12-21 22:54:26 +03:00
Triang3l
72e9ac5c28 [GPU] Shader translator: More memexport validation 2018-12-21 22:24:09 +03:00
Triang3l
73baaa8e89 [GPU] Gather eA/eM# writes in shader translator 2018-12-21 10:06:41 +03:00
Triang3l
090bf8e353 [D3D12] Change RT in the title to something less ambiguous and more googlable 2018-12-20 20:48:15 +03:00
Triang3l
adc0eb87f6 [GPU] Gather used memexport constants in shader translator 2018-12-20 10:14:18 +03:00
Triang3l
dc0b468ea8 Merge branch 'master' into d3d12 2018-12-19 22:51:26 +03:00
Triang3l
486a5725e3 [GPU] xenos.h: tessellation, memexport constant 2018-12-19 22:50:43 +03:00
Triang3l
c84511a5f1 [GPU/D3D12] Update tessellation enums 2018-12-19 18:23:54 +03:00
Triang3l
cbba86fcf0 [D3D12] Split DXBC shader translator into multiple files 2018-12-19 14:24:16 +03:00
Triang3l
2de0e26606 [D3D12] DXBC: Remove ugly useless indexable temp fallback 2018-12-16 13:03:03 +03:00
Triang3l
574f85cc15 [D3D12] Refactoring: DXBC -> Dxbc 2018-12-14 13:25:07 +03:00
Triang3l
952819ed87 [D3D12] Don't 4KB-align sizes of resolve destinations 2018-12-13 15:22:16 +03:00
Triang3l
2b55ec86ea [GPU] Shader Compiler: Expose domain shader output 2018-12-13 14:52:50 +03:00
Triang3l
2b646ff425 [D3D12] Fake per-edge tessellation with continuous 2018-12-12 22:12:32 +03:00
Triang3l
7698944673 [D3D12] Swap red and blue in 8bpp gamma ramp 2018-12-09 15:53:57 +03:00
Triang3l
1ee3ed03fd [D3D12] DXBC: Skip loading and some ALU ops for identical operands 2018-12-09 00:20:13 +03:00
Triang3l
352a443c67 [D3D12] DXBC: Small cleanup of something ugly in subs_prev 2018-12-08 19:18:56 +03:00
Triang3l
e1f0e9c84a [D3D12] DXBC: Slightly shorten SM3 mul behavior emulation 2018-12-08 16:42:30 +03:00
Triang3l
9427667a27 [D3D12] Experimental 2x resolution scale 2018-12-06 10:38:13 +03:00
Triang3l
132af3e266 [D3D12] DXBC: Don't skip invariant driver optimizations 2018-12-04 12:29:27 +03:00
Triang3l
bb53d722f9 [D3D12] Don't use switch in shaders on Intel, log GPU name 2018-12-03 16:31:49 +03:00
Triang3l
5b9e4b5886 Merge branch 'master' into d3d12 2018-11-27 11:05:14 +03:00
Triang3l
f634e94227 [D3D12] ROV: Don't mark Z of PS SV_Position as used in dcl 2018-11-26 20:53:34 +03:00
gibbed
2398b1b8f4 [Vulkan] Use epsilon equality for checking rectangle list form. 2018-11-26 11:51:02 -06:00
gibbed
af206addd1 Optimize SPIRV code generated via genspirv command. 2018-11-26 11:49:36 -06:00
Triang3l
355d33dadd [D3D12] Rename feature gflags 2018-11-25 23:25:56 +03:00
Triang3l
9a58841219 [D3D12] ROV: Use MSAA instead of SSAA 2018-11-25 16:37:38 +03:00
Triang3l
5c1efe7b9a Merge branch 'master' into d3d12 2018-11-24 16:26:27 +03:00
gibbed
d87ae26895 [CI] Fix mspack linking even more. 2018-11-23 17:58:38 -06:00
Triang3l
da280347c4 Merge branch 'master' into d3d12 2018-11-22 21:01:05 +03:00
Margen67
896ac4a682 Update documentation. 
- Convert http to https, provide archive link when possible.
- Made CPU-JIT.png more readable on dark themes;
Added a white background so there isn't black text on a black
background.
 2018-11-22 09:20:09 -06:00
gibbed
1ba5dd5eb1 Use platform-specific user directory to store content. Create a file named portable.txt next to xenia.exe to restore previous behavior. 2018-11-21 18:07:45 -06:00
Triang3l
14b623465c [D3D12] ROV: ForcedSampleCount=1 for safety 2018-11-21 20:53:11 +03:00
Triang3l
70fae20072 [D3D12] Apply scissor to resolve regions 2018-11-21 17:15:09 +03:00
Triang3l
c061836649 [D3D12] Enable ROV by default 2018-11-20 21:30:36 +03:00
Triang3l
b0b1e684f7 [D3D12] Fix UAV binding in EDRAM clear root signature 2018-11-20 21:29:04 +03:00
Triang3l
d35be635d6 Merge branch 'master' of github.com:xenia-project/xenia into d3d12 2018-11-18 22:21:32 +03:00
Triang3l
7fa453c813 [GPU] Fix 1-component ALU instruction swizzle (hopefully) 2018-11-18 22:20:43 +03:00
Triang3l
66a37c0cc3 [D3D12] ROV: Aliasing and bounds checking, retc instead of discard 2018-11-17 17:15:15 +03:00
Triang3l
6901c3ea17 [D3D12] DXBC: Fix operands in scalar multiplication zero check 2018-11-16 19:25:24 +03:00
Triang3l
e46244a996 [D3D12] Put shared memory in PS resource state because vfetch seems allowed in PS 2018-11-16 13:12:51 +03:00
Triang3l
38f421e89f [D3D12] GPUTEXTUREFORMAT_6_5_5 as RBG 2018-11-16 12:56:19 +03:00
Triang3l
e1d771ab9c [D3D12] GPUTEXTUREFORMAT_11_11_10 support 2018-11-14 17:02:19 +03:00