Commit Graph

50 Commits

Author SHA1 Message Date
Herman S.
2912da02fe [D3D12] Fix gamma_unorm16 render target transfer shaders
Gamma stored as R16G16B16A16_UNORM is 64bpp in host memory but
represents a single 32bpp pixel, unlike true 64bpp formats which pack
two 32bpp pixels together. Separate dest_is_gamma_unorm16 from
dest_is_64bpp to avoid incorrect coordinate transforms.

Add output paths for gamma_unorm16 destinations:
- gamma→gamma: direct passthrough (already linear in R16G16B16A16)
- k_8_8_8_8→gamma: convert gamma-encoded source to linear
- Cross-format packed EDRAM: midpoint encoding to survive UNORM16
  quantization round-trip through PreSaturatedLinearToPWLGamma

Fixes red bleeding in Halo Reach, image halving in Just Cause 2,
Portal not rendering, and black rock/plant textures in Halo Reach.
2026-03-06 23:05:39 +09:00
Herman S.
65d42843b6 Merge remote-tracking branch 'xenia-master/master' into canary_experimental 2026-03-06 23:05:24 +09:00
Triang3l
95a5c3ee25 [GPU/WGF] Bind EDRAM to resolve dumping via ByteAddressBuffer
Simplifies binding by eliminating the need to switch between 32-bit and
64-bit views, and makes it possible to bind the EDRAM via a root descriptor
on Direct3D 12.
2026-02-18 22:40:20 +03:00
Triang3l
80dad41454 [GPU/WGF] Use ByteAddressBuffer in precompiled shaders
Drivers and hardware may provide more optimal paths for untyped buffers
compared to typed.

Also, ByteAddressBuffer may be bound via a root descriptor in Direct3D 12,
greatly simplifying the binding logic.

ByteAddressBuffer also doesn't have the 128 * 2^20 element count limit that
typed and structured buffers have, and doesn't require the structure stride
to be specified at resource creation time in Direct3D 11.
2026-02-17 23:28:42 +03:00
Herman S.
ef505fbe3d [Vulkan] add no_discard_stencil_in_transfer_pipelines support 2026-02-17 17:54:01 +09:00
Triang3l
c7f61342d7 [GPU/D3D12] Convert gamma-as-linear red to gamma in transfers to stencil
Co-authored-by: Herman S. <429230+has207@users.noreply.github.com>
2026-01-20 12:53:20 +03:00
Triang3l
0a19234b4e [GPU/D3D12] Add forgotten gamma conversion format check 2026-01-19 21:08:15 +03:00
Triang3l
cec9ca0ef2 [GPU] 8-bit PWL gamma RT as linear 16-bit UNorm on the host
With render target HLE, directly store linear values as R16G16B16A16_UNORM
without gamma conversion, as this format provides more than enough bits
(need at least 11 per component due to the maximum scale being 2^3 in the
piecewise linear gamma curve) to represent linear values without precision
loss.

This makes blending work correctly in linear space, improving quality of
transparency, lighting passes, and fixing issues such as transparent parts
of impact and footstep decals in 4D5307E6 being bright instead.

The new behavior is enabled by default, as it hugely improves the accuracy
of emulation of this format, that is pretty commonplace in Xbox 360 games,
with likely just a small GPU memory and bandwidth usage increase, compared
to the alternatives that were previously available on the HLE RB path.

It's currently implemented only on Direct3D 12, as most of the current GPU
emulation code is planned to be phased out and redone, and no methods other
than 8-bit with pre-conversion were implemented on Vulkan previously.

To implement on Vulkan later, same conversion as in the Direct3D 12
implementation will need to be done in ownership transfer and resolve
shaders. Currently it's somewhat inconvenient to decouple the conversion
functions in `SpirvShaderTranslator` from an instance of the translator due
to vector constant usage. Later, simpler SPIR-V generation functions may be
added (`spv::Builder` usage in general is overly verbose).

The previously default method (8-bit storage with pre-conversion in shaders
and incorrect blending) can be re-enabled by setting the
"gamma_render_target_as_unorm16" configuration option to `false`. This may
be useful if the game, for instance, switches between 8_8_8_8_GAMMA and
8_8_8_8 formats for the same data frequently, as switching will result in
EDRAM range ownership transfer data copying now. Also, the old path is
preserved for Vulkan devices not supporting R16G16B16A16_UNORM with
blending.

The other workaround that was available previously, replacing the PWL
encoding with host hardware sRGB with linear-space blending in render
target management and in texture fetching, was also inherently inaccurate
in many ways (especially when games have their own PWL encoding math, like
4541080F that displayed incorrect colors on the loading screen), and
required tracking of the encoding needed for ranges in the memory.

The sRGB workaround therefore was deleted in this commit, greatly
simplifying the code in the parts of render target, texture and memory
management and shader generation that were involved in it.
2026-01-18 16:22:22 +03:00
yippeeeyay
2b77c4c08a [D3D12] Simplify Intel Arc GPU checking 2025-12-07 19:09:36 +01:00
Gliniak
37e3fe9eb6 [D3D12] Default to RTV on Intel ARC GPUs 2025-08-03 22:26:39 +02:00
Margen67
4cb783bf22 Header cleanup 2025-07-19 14:42:21 -07:00
Gliniak
3ba31d9f9a Revert "[D3D12] Changed default resource state based on GPU Validation"
This causes unexpected artifacts on 10 series Nvidia GPUs

This reverts commit 7566871220.
2025-05-04 08:57:42 +02:00
Gliniak
7566871220 [D3D12] Changed default resource state based on GPU Validation
- This prevents GBV from spamming warnings
2025-04-22 19:31:31 +02:00
Xphalnos
47f327e848 [Misc] Replaced const with constexpr where possible 2025-04-08 19:32:17 +02:00
Xphalnos
7479ccc292 [Misc] Fix Some Warnings on Clang Build with Windows + Adding constexpr 2025-03-27 17:52:18 +01:00
Xphalnos
5f918ef28d [Misc] Replaced const with constexpr where possible 2025-03-25 19:50:37 +01:00
Gliniak
3318ab5d4c [3PP] Uplifted FMT version and adjusted messages 2024-12-12 20:28:11 +01:00
chss95cs@gmail.com
a63f424c0a Directly check PEB for IsDebuggerAttached
Add constexpr getters to magicdiv class so it can be used from jitted x64/dxbc
Track the guest return address as well for guest/host sync, if multiple entries have the same guest stack find the first one with a matching guest retaddr. this fixes epic mickey 2 (which the previous guest-stack change had allowed to go ingame for a bit) and potentially also a crash in fable3.
Break if under debugger when stackpoints are overflowed

Add much more useful output for host exceptions, print out xenia_canary.exe relative offsets if exception is in module, formatmessage for ntstatus/win32err, strerror

Minor d3d12 microoptimization, instead of doing SetEventOnCompletion + WaitForSingleObject do SetEventOnCompletion w/ nullptr so that the wait happens in kernel mode, avoiding two extra context switches

add unimplemented kernel functions:
ExAllocatePoolWithTag
ObReferenceObject

ObDereferenceObject has no return value.
Log a message when ObDereferenceObject/Reference receive unregistered guest kernel objects
gave ObLookupThreadByThreadId its correct error status
hoist object_types initialization out of ObReferenceObjectByHandle
Fix out parameter values on error for a few kernel funcs
add note about msr to KeSetCurrentStackPointers
add X_STATUS_OBJECT_TYPE_MISMATCH check for xeNtSetEvent
add msr_mask field to X_KPCR
2022-12-04 12:38:19 -08:00
chss95cs@gmail.com
20638c2e61 use Sleep(0) instead of SwitchToThread, should waste less power and help the os with scheduling.
PM4 buffer handling made a virtual member of commandprocessor, place the implementation/declaration into reusable macro files. this is probably the biggest boost here.
Optimized SET_CONSTANT/ LOAD_CONSTANT pm4 ops based on the register range they start writing at, this was also a nice boost

Expose X64 extension flags to code outside of x64 backend, so we can detect and use things like avx512, xop, avx2, etc in normal code
Add freelists for HIR structures to try to reduce the number of last level cache misses during optimization (currently disabled... fixme later)

Analyzed PGO feedback and reordered branches, uninlined functions, moved code out into different functions based on info from it in the PM4 functions, this gave like a 2% boost at best.

Added support for the db16cyc opcode, which is used often in xb360 spinlocks. before it was just being translated to nop, now on x64 we translate it to _mm_pause but may change that in the future to reduce cpu time wasted

texture util - all our divisors were powers of 2, instead we look up a shift. this made texture scaling slightly faster, more so on intel processors which seem to be worse at int divs. GetGuestTextureLayout is now a little faster, although it is still one of the heaviest functions in the emulator when scaling is on.

xe_unlikely_mutex was not a good choice for the guest clock lock, (running theory) on intel processors another thread may take a significant time to update the clock? maybe because of the uint64 division? really not sure, but switched it to xe_mutex. This fixed audio stutter that i had introduced to 1 or 2 games, fixed performance on that n64 rare game with the monkeys.
Took another crack at DMA implementation, another failure.
Instead of passing as a parameter, keep the ringbuffer reader as the first member of commandprocessor so it can be accessed through this
Added macro for noalias
Applied noalias to Memory::LookupHeap. This reduced the size of the executable by 7 kb.
Reworked kernel shim template, this shaved like 100kb off the exe and eliminated the indirect calls from the shim to the actual implementation. We still unconditionally generate string representations of kernel calls though :(, unless it is kHighFrequency

Add nvapi extensions support, currently unused. Will use CPUVISIBLE memory at some point
Inserted prefetches in a few places based on feedback from vtune.
Add native implementation of SHA int8 if all elements are the same

Vectorized comparisons for SetViewport, SetScissorRect
Vectorized ranged comparisons for WriteRegister
Add XE_MSVC_ASSUME
Move FormatInfo::name out of the structure, instead look up the name in a different table. Debug related data and critical runtime data are best kept apart
Templated UpdateSystemConstantValues based on ROV/RTV and primitive_polygonal
Add ArchFloatMask functions, these are for storing the results of floating point comparisons without doing costly float->int pipeline transfers (vucomiss/setb)
Use floatmasks in UpdateSystemConstantValues for checking if dirty, only transfer to int at end of function.
Instead of dirty |= (x == y) in UpdateSystemConstantValues, now we do dirty_u32 |= (x^y). if any of them are not equal, dirty_u32 will be nz, else if theyre all equal it will be zero. This is more friendly to register renaming and the lack of dependencies on EFLAGS lets the compiler reorder better
Add PrefetchSamplerParameters to D3D12TextureCache
use PrefetchSamplerParameters in UpdateBindings to eliminate cache misses that vtune detected

Add PrefetchTextureBinding to D3D12TextureCache
Prefetch texture bindings to get rid of more misses vtune detected (more accesses out of order with random strides)
Rewrote DMAC, still terrible though and have disabled it for now.
Replace tiny memcmp of 6 U64 in render_target_cache with inline loop, msvc fails to make it a loop and instead does a thunk to their memcmp function, which is optimized for larger sizes

PrefetchTextureBinding in AreActiveTextureSRVKeysUpToDate
Replace memcmp calls for pipelinedescription with handwritten cmp
Directly write some registers that dont have special handling in PM4 functions
Changed EstimateMaxY to try to eliminate mispredictions that vtune was reporting, msvc ended up turning the changed code into a series of blends

in ExecutePacketType3_EVENT_WRITE_EXT, instead of writing extents to an array on the stack and then doing xe_copy_and_swap_16 of the data to its dest, pre-swap each constant and then store those. msvc manages to unroll that into wider stores
stop logging XE_SWAP every time we receive XE_SWAP, stop logging the start and end of each viz query

Prefetch watch nodes in FireWatches based on feedback from vtune
Removed dead code from texture_info.cc
NOINLINE on GpuSwap, PGO builds did it so we should too.
2022-09-11 14:14:48 -07:00
chss95cs@gmail.com
cb85fe401c Huge set of performance improvements, combined with an architecture specific build and clang-cl users have reported absurd gains over master for some gains, in the range 50%-90%
But for normal msvc builds i would put it at around 30-50%
Added per-xexmodule caching of information per instruction, can be used to remember what code needs compiling at start up
Record what guest addresses wrote mmio and backpropagate that to future runs, eliminating dependence on exception trapping. this makes many games like h3 actually tolerable to run under a debugger
fixed a number of errors where temporaries were being passed by reference/pointer
Can now be compiled with clang-cl 14.0.1, requires -Werror off though and some other solution/project changes.
Added macros wrapping compiler extensions like noinline, forceinline, __expect, and cold.
Removed the "global lock" in guest code completely. It does not properly emulate the behavior of mfmsrd/mtmsr and it seriously cripples amd cpus. Removing this yielded around a 3x speedup in Halo Reach for me.
Disabled the microprofiler for now. The microprofiler has a huge performance cost associated with it. Developers can re-enable it in the base/profiling header if they really need it
Disable the trace writer in release builds. despite just returning after checking if the file was open the trace functions were consuming about 0.60% cpu time total
Add IsValidReg, GetRegisterInfo is a huge (about 45k) branching function and using that to check if a register was valid consumed a significant chunk of time
Optimized RingBuffer::ReadAndSwap and RingBuffer::read_count. This gave us the largest overall boost in performance. The memcpies were unnecessary and one of them was always a no-op
Added simplification rules for multiplicative patterns like (x+x), (x<<1)+x
For the most frequently called win32 functions i added code to call their underlying NT implementations, which lets us skip a lot of MS code we don't care about/isnt relevant to our usecases
^this can be toggled off in the platform_win header
handle indirect call true with constant function pointer, was occurring in h3
lookup host format swizzle in denser array
by default, don't check if a gpu register is unknown, instead just check if its out of range. controlled by a cvar
^looking up whether its known or not took approx 0.3% cpu time
Changed some things in /cpu to make the project UNITYBUILD friendly
The timer thread was spinning way too much and consuming a ton of cpu, changed it to use a blocking wait instead
tagged some conditions as XE_UNLIKELY/LIKELY based on profiler feedback (will only affect clang builds)
Shifted around some code in CommandProcessor::WriteRegister based on how frequently it was executed
added support for docdecaduple precision floating point so that we can represent our performance gains numerically
tons of other stuff im probably forgetting
2022-08-13 12:59:00 -07:00
Triang3l
3c12814276 [GPU] EDRAM looped addressing (resolves #2031) 2022-07-22 23:51:50 +03:00
Triang3l
14fdf4b270 [GPU] Up to 7x7 resolution scaling 2022-07-17 20:41:50 +03:00
Triang3l
7a4732e14f [GPU] XeSL swap shaders 2022-06-24 23:24:30 +03:00
Triang3l
cbf0476d42 [D3D12] Don't round float24 depth when it's known to be exact 2022-06-22 13:14:38 +03:00
Triang3l
7869b080d3 [D3D12] Truncate depth to float24 in EDRAM range ownership transfers and resolves by default
Doesn't ruin the "greater or equal" depth test in subsequent rendering passes if precision is lost, unlike rounding to the nearest
2022-06-22 12:53:09 +03:00
Triang3l
e2f632f8fa [D3D12] Use udiv by constant tile size + minor transfer cleanup
Drivers compile that to a multiplication and a shift anyway.
2022-06-20 22:39:30 +03:00
Triang3l
207e11c8d2 [GPU] Separate range arguments for fixed16 RG and RGBA in GetResolveInfo
On Vulkan, when snorm16 in unsupported, these formats may be emulated as float16, which natively can represent a wide range of numbers including -32 to 32 with blending. However, R16G16_SNORM and R16G16B16A16_SNORM are two separate formats, which may have different support on the device.
2022-06-20 12:29:45 +03:00
Triang3l
84fcd5defa [GPU] Fix resolve destination offset and extent calculation 2022-06-02 21:47:30 +03:00
Triang3l
efd7ef212a [D3D12] 128 megatexel limit explanation based on the spec [ci skip] 2022-05-31 23:23:10 +03:00
Triang3l
d280b3953d [GPU] Texture object/binding management to common superclass 2022-05-14 16:18:10 +03:00
Triang3l
e3425b242e [DXBC] Both v[#] and v[#][#] operands for HS and GS 2022-05-07 16:17:17 +03:00
Triang3l
7a89ad16a6 [D3D12] Update D3D12RenderTargetCache::Update write mask argument name 2022-05-02 23:16:18 +03:00
Triang3l
0fd578cafd [GPU] Get unclipped draw height by running VS on the CPU 2022-04-28 22:25:25 +03:00
Triang3l
5ec0c92601 [GPU] Ignore z_enable for !z_write_enable && z_func == ALWAYS 2022-04-27 21:46:29 +03:00
Triang3l
c4eae232f1 [D3D12] Fixes/cleanup for render targets and barriers 2022-04-02 22:44:10 +03:00
Triang3l
3a07559df9 [GPU] XeSL host depth store and VS passthrough shaders 2022-03-27 16:15:53 +03:00
Triang3l
32ab1a2df1 [D3D12] Minor RT code style/comments cleanup 2022-03-22 21:48:26 +03:00
Triang3l
ee8e71cea8 [D3D12] RT dump: Fix r# allocation 2022-03-22 21:41:44 +03:00
Triang3l
920704c71a [D3D12] RT transfer: Same front/back stencil ops 2022-03-22 21:39:06 +03:00
Triang3l
fe3f0f26e4 [UI] Image post-processing and full presentation/window rework
[GPU] Add FXAA post-processing
[UI] Add FidelityFX FSR and CAS post-processing
[UI] Add blue noise dithering from 10bpc to 8bpc
[GPU] Apply the DC PWL gamma ramp closer to the spec, supporting fully white color
[UI] Allow the GPU CP thread to present on the host directly, bypassing the UI thread OS paint event
[UI] Allow variable refresh rate (or tearing)
[UI] Present the newest frame (restart) on DXGI
[UI] Replace GraphicsContext with a far more advanced Presenter with more coherent surface connection and UI overlay state management
[UI] Connect presentation to windows via the Surface class, not native window handles
[Vulkan] Switch to simpler Vulkan setup with no instance/device separation due to interdependencies and to pass fewer objects around
[Vulkan] Lower the minimum required Vulkan version to 1.0
[UI/GPU] Various cleanup, mainly ComPtr usage
[UI] Support per-monitor DPI awareness v2 on Windows
[UI] DPI-scale Dear ImGui
[UI] Replace the remaining non-detachable window delegates with unified window event and input listeners
[UI] Allow listeners to safely destroy or close the window, and to register/unregister listeners without use-after-free and the ABA problem
[UI] Explicit Z ordering of input listeners and UI overlays, top-down for input, bottom-up for drawing
[UI] Add explicit window lifecycle phases
[UI] Replace Window virtual functions with explicit desired state, its application, actual state, its feedback
[UI] GTK: Apply the initial size to the drawing area
[UI] Limit internal UI frame rate to that of the monitor
[UI] Hide the cursor using a timer instead of polling due to no repeated UI thread paints with GPU CP thread presentation, and only within the window
2022-01-29 13:22:03 +03:00
Triang3l
38b4741c8f [GPU] Mostly generic, not square-only resolution scaling 2021-12-11 21:55:33 +03:00
Triang3l
e720e0a540 [Code] Remove game names from code comments (most of at least) 2021-09-05 21:27:40 +03:00
Triang3l
3a2c7894d2 [D3D12] Remove unused D3D12RenderTargetCache ref from D3D12RenderTarget 2021-06-19 14:06:37 +03:00
Triang3l
8e83042bdf [GPU] Fix host_depth_store_2xmsaa CS after 2x MSAA sample swap 2021-06-14 19:12:12 +03:00
Triang3l
357aa1cdd3 [GPU] Fix RT view and pipeline sRGB mismatch 2021-06-14 17:30:56 +03:00
Triang3l
3f156f26c4 [D3D12] Take 0 being bottom-right sample with 2x MSAA in D3D12 into account 2021-06-06 20:58:50 +03:00
Triang3l
12a907bfa5 [GPU] Shaders to common, xb buildshaders instead of buildhlsl 2021-06-05 18:53:53 +03:00
Triang3l
bb55bb3e70 [D3D12] Make ROV the default RT path on Intel due to stencil 2021-04-28 20:53:07 +03:00
Triang3l
71fbfdb63e [D3D12] Fix non-ROV clearing always giving 'failed in backend' 2021-04-28 17:27:57 +03:00
Triang3l
913e1e949c [GPU] Ownership-transfer-based RT cache, 3x3 resolution scaling
The ROV path is also disabled by default because of lower performance
2021-04-26 22:12:09 +03:00