Triang3l
|
ecc056912d
|
[D3D12] Don't drop draw calls with no render targets
|
2019-04-12 16:59:45 +03:00 |
|
Triang3l
|
93a18a517b
|
[D3D12] Place UAV barriers for the EDRAM ROV when layout changes
|
2019-04-12 15:59:09 +03:00 |
|
Triang3l
|
45cee3f871
|
[D3D12] Don't create RT store pipelines with ROV
|
2019-04-11 12:05:13 +03:00 |
|
Triang3l
|
88c594ca3b
|
[D3D12] Fix RB_COPY_DEST_PITCH handling in ResolveCopy
|
2019-04-10 22:35:05 +03:00 |
|
Triang3l
|
5e30f3a947
|
[D3D12] User clip planes and constant/signature refactoring
|
2019-04-10 16:37:06 +03:00 |
|
Triang3l
|
8c56d5cb98
|
[D3D12] Fix lint failure in RenderTargetCache::BeginFrame
|
2019-04-09 23:04:13 +03:00 |
|
Triang3l
|
4e8e75c549
|
[D3D12] Remove TODO for initial EDRAM clear since Windows clears allocations anyway
|
2019-04-09 19:45:35 +03:00 |
|
Triang3l
|
959b8ef19e
|
[D3D12] Draw rectangles by mirroring one vertex across diagonal
|
2019-04-09 17:19:47 +03:00 |
|
Triang3l
|
6db0ad663b
|
[D3D12] mb_used -> used_mb in the profiler
|
2019-04-05 15:31:59 +03:00 |
|
Triang3l
|
d0c8725270
|
[D3D12] Limit texture memory usage with LRU deletion
|
2019-04-05 15:19:16 +03:00 |
|
Triang3l
|
5582e63ef1
|
[D3D12] Resolve 16-bit RTs to unorm textures, not snorm
|
2019-03-07 11:21:39 +03:00 |
|
Triang3l
|
7049d52dbb
|
[D3D12] Display texture cache size in the profiler
|
2019-03-05 10:26:40 +03:00 |
|
Triang3l
|
57e8f05234
|
[D3D12] Make RG16/RGBA16 RTVs range switchable
|
2019-01-29 14:39:04 +03:00 |
|
Triang3l
|
61fd5a6dc2
|
[D3D12] Replicate red channel of single-channel textures
|
2019-01-26 14:11:09 +03:00 |
|
Triang3l
|
ba7b6d6081
|
[D3D12] Memexport CPU readback, disabled by default
|
2019-01-25 16:33:25 +03:00 |
|
Triang3l
|
4a3245650f
|
[D3D12] Optional non-GS path for quads for PIX
|
2019-01-25 15:09:58 +03:00 |
|
Triang3l
|
9dd62c1e15
|
[D3D12] Alpha to coverage (w/o dithering) with RTV, tiny AtoC fixes
|
2019-01-21 23:41:47 +03:00 |
|
Triang3l
|
0a9feb5eca
|
[D3D12] ROV: Alpha to coverage (without dithering)
|
2019-01-21 21:28:26 +03:00 |
|
Triang3l
|
0fc8497905
|
[D3D12] Fix debug config crash in back buffer stretching code
|
2019-01-19 14:48:46 +03:00 |
|
Triang3l
|
b7bcdf3e8b
|
[D3D12] Pre-create EDRAM and shared memory buffer descriptors
|
2019-01-17 16:39:51 +03:00 |
|
Triang3l
|
cf7c981991
|
[D3D12] Cache SRV descriptors in the texture cache to copy instead of creating
|
2019-01-16 19:06:11 +03:00 |
|
Triang3l
|
cf3ce4f98b
|
[D3D12] Unhardcode forgotten pipeline creation thread count
|
2019-01-15 21:04:17 +03:00 |
|
Triang3l
|
a1a1110784
|
[D3D12] Non-indexed line loops
|
2019-01-15 14:19:59 +03:00 |
|
Triang3l
|
17dfd84f71
|
[D3D12] Free two alphatest-related system constant dwords
|
2019-01-15 12:58:36 +03:00 |
|
Triang3l
|
b8d1bb740b
|
[GPU/D3D12] Fix CTX1 component order
|
2019-01-12 14:28:32 +03:00 |
|
Triang3l
|
ef523823d5
|
[D3D12] Force early Z with DSV, fix blend disabled flag in rb_colorcontrol ignored
|
2019-01-11 17:07:33 +03:00 |
|
Triang3l
|
d7ed044be1
|
[D3D12] Don't cull points and rectangles
|
2019-01-09 16:25:03 +03:00 |
|
Triang3l
|
8ad12480a4
|
[D3D12] Copy index buffer to a scratch buffer for memexporting draws
|
2019-01-09 13:19:49 +03:00 |
|
Triang3l
|
aabe6dec9c
|
[D3D12] Fix log level of pipeline creation messages
|
2019-01-08 14:14:14 +03:00 |
|
Triang3l
|
6c48f209a1
|
[D3D12] Fix 7e3 and 20e4 denormal conversion
|
2019-01-06 15:10:55 +03:00 |
|
Triang3l
|
1523a1f662
|
[D3D12] Use 3/4 of logical cores for pipeline creation, cleanup pipeline log messages
|
2019-01-04 14:30:26 +03:00 |
|
Triang3l
|
890228b6f3
|
[D3D12] Prototype multithreaded PSO creation
|
2019-01-04 00:30:11 +03:00 |
|
Triang3l
|
364cae6cc8
|
[D3D12] Use deferred command list
|
2019-01-03 15:08:49 +03:00 |
|
Triang3l
|
f0c662fa1e
|
[D3D12] Deferred command list class
|
2019-01-02 23:46:24 +03:00 |
|
Triang3l
|
a97fc28ee2
|
[D3D12] Use multimap for pipelines
|
2019-01-01 23:13:26 +03:00 |
|
Triang3l
|
1cea4062c0
|
[D3D12] Rewrite pipeline cache for compact storage of pipeline descriptions
|
2019-01-01 22:20:50 +03:00 |
|
Triang3l
|
317e5c3ce2
|
[D3D12] Some stats in the profiler, tweak tiled buffer heap sizes
|
2018-12-30 15:09:58 +03:00 |
|
Triang3l
|
87d663d7e0
|
[D3D12] Disable adaptive tessellation temporarily because of cracks
|
2018-12-29 21:12:21 +03:00 |
|
Triang3l
|
928e46c8b2
|
[D3D12] Adaptive tessellation of triangle patches
|
2018-12-29 20:53:41 +03:00 |
|
Triang3l
|
14476e5453
|
[D3D12] Rename 2_10_10_10 AS_16 RT format to AS_10
|
2018-12-29 14:59:10 +03:00 |
|
Triang3l
|
cbfc00f80e
|
[D3D12] Debug option to display tessellation as wireframe
|
2018-12-28 14:37:39 +03:00 |
|
Triang3l
|
ed09cac440
|
[D3D12] DXBC: vfetch RoundIndex, vertex index signedness fixes
|
2018-12-28 08:11:34 +03:00 |
|
Triang3l
|
e803ee84d5
|
[D3D12] Bind shared memory as UAV with memexport
|
2018-12-22 15:39:47 +03:00 |
|
Triang3l
|
6025599d3b
|
[D3D12] Request memory for memexport in shared memory
|
2018-12-22 00:57:31 +03:00 |
|
Triang3l
|
090bf8e353
|
[D3D12] Change RT in the title to something less ambiguous and more googlable
|
2018-12-20 20:48:15 +03:00 |
|
Triang3l
|
c84511a5f1
|
[GPU/D3D12] Update tessellation enums
|
2018-12-19 18:23:54 +03:00 |
|
Triang3l
|
574f85cc15
|
[D3D12] Refactoring: DXBC -> Dxbc
|
2018-12-14 13:25:07 +03:00 |
|
Triang3l
|
952819ed87
|
[D3D12] Don't 4KB-align sizes of resolve destinations
|
2018-12-13 15:22:16 +03:00 |
|
Triang3l
|
2b646ff425
|
[D3D12] Fake per-edge tessellation with continuous
|
2018-12-12 22:12:32 +03:00 |
|
Triang3l
|
7698944673
|
[D3D12] Swap red and blue in 8bpp gamma ramp
|
2018-12-09 15:53:57 +03:00 |
|