1493 lines
45 KiB
C++
1493 lines
45 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include <xenia/gpu/d3d11/d3d11_shader.h>
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#include <xenia/gpu/gpu-private.h>
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#include <xenia/gpu/xenos/ucode.h>
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#include <d3dcompiler.h>
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using namespace xe;
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using namespace xe::gpu;
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using namespace xe::gpu::d3d11;
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using namespace xe::gpu::xenos;
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namespace {
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const uint32_t MAX_INTERPOLATORS = 16;
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const int OUTPUT_CAPACITY = 64 * 1024;
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} // anonymous namespace
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struct xe::gpu::d3d11::Output {
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char buffer[OUTPUT_CAPACITY];
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size_t capacity;
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size_t offset;
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Output() :
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capacity(OUTPUT_CAPACITY),
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offset(0) {
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buffer[0] = 0;
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}
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void append(const char* format, ...) {
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va_list args;
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va_start(args, format);
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int len = xevsnprintfa(
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buffer + offset, capacity - offset, format, args);
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va_end(args);
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offset += len;
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buffer[offset] = 0;
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}
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};
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D3D11Shader::D3D11Shader(
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ID3D11Device* device,
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XE_GPU_SHADER_TYPE type,
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const uint8_t* src_ptr, size_t length,
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uint64_t hash) :
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translated_src_(NULL),
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Shader(type, src_ptr, length, hash) {
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device_ = device;
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device_->AddRef();
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}
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D3D11Shader::~D3D11Shader() {
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if (translated_src_) {
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xe_free(translated_src_);
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}
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XESAFERELEASE(device_);
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}
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void D3D11Shader::set_translated_src(char* value) {
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if (translated_src_) {
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xe_free(translated_src_);
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}
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translated_src_ = xestrdupa(value);
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}
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ID3D10Blob* D3D11Shader::Compile(const char* shader_source) {
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// TODO(benvanik): pick shared runtime mode defines.
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D3D10_SHADER_MACRO defines[] = {
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"TEST_DEFINE", "1",
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0, 0,
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};
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uint32_t flags1 = 0;
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flags1 |= D3D10_SHADER_DEBUG;
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flags1 |= D3D10_SHADER_ENABLE_STRICTNESS;
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uint32_t flags2 = 0;
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// Create a name.
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const char* base_path = "";
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if (FLAGS_dump_shaders.size()) {
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base_path = FLAGS_dump_shaders.c_str();
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}
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char file_name[XE_MAX_PATH];
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xesnprintfa(file_name, XECOUNT(file_name),
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"%s/gen_%.16XLL.%s",
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base_path,
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hash_,
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type_ == XE_GPU_SHADER_TYPE_VERTEX ? "vs" : "ps");
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if (FLAGS_dump_shaders.size()) {
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FILE* f = fopen(file_name, "w");
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fprintf(f, shader_source);
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fprintf(f, "\n\n");
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fprintf(f, "/*\n");
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fprintf(f, disasm_src_);
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fprintf(f, " */\n");
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fclose(f);
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}
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// Compile shader to bytecode blob.
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ID3D10Blob* shader_blob = 0;
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ID3D10Blob* error_blob = 0;
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HRESULT hr = D3DCompile(
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shader_source, strlen(shader_source),
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file_name,
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defines, NULL,
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"main",
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type_ == XE_GPU_SHADER_TYPE_VERTEX ?
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"vs_5_0" : "ps_5_0",
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flags1, flags2,
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&shader_blob, &error_blob);
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if (error_blob) {
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char* msg = (char*)error_blob->GetBufferPointer();
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XELOGE("D3D11: shader compile failed with %s", msg);
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}
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XESAFERELEASE(error_blob);
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if (FAILED(hr)) {
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return NULL;
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}
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return shader_blob;
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}
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D3D11VertexShader::D3D11VertexShader(
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ID3D11Device* device,
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const uint8_t* src_ptr, size_t length,
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uint64_t hash) :
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handle_(0), input_layout_(0),
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D3D11Shader(device, XE_GPU_SHADER_TYPE_VERTEX,
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src_ptr, length, hash) {
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}
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D3D11VertexShader::~D3D11VertexShader() {
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XESAFERELEASE(input_layout_);
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XESAFERELEASE(handle_);
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}
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int D3D11VertexShader::Prepare(xe_gpu_program_cntl_t* program_cntl) {
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if (handle_) {
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return 0;
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}
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// TODO(benvanik): look in file based on hash/etc.
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void* byte_code = NULL;
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size_t byte_code_length = 0;
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// Translate and compile source.
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const char* shader_source = Translate(program_cntl);
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if (!shader_source) {
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return 1;
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}
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ID3D10Blob* shader_blob = Compile(shader_source);
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if (!shader_blob) {
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return 1;
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}
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byte_code_length = shader_blob->GetBufferSize();
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byte_code = xe_malloc(byte_code_length);
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xe_copy_struct(
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byte_code, shader_blob->GetBufferPointer(), byte_code_length);
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XESAFERELEASE(shader_blob);
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// Create shader.
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HRESULT hr = device_->CreateVertexShader(
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byte_code, byte_code_length,
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NULL,
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&handle_);
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if (FAILED(hr)) {
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XELOGE("D3D11: failed to create vertex shader");
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xe_free(byte_code);
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return 1;
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}
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// Create input layout.
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size_t element_count = fetch_vtxs_.size();
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D3D11_INPUT_ELEMENT_DESC* element_descs =
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(D3D11_INPUT_ELEMENT_DESC*)xe_alloca(
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sizeof(D3D11_INPUT_ELEMENT_DESC) * element_count);
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int n = 0;
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for (std::vector<instr_fetch_vtx_t>::iterator it = fetch_vtxs_.begin();
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it != fetch_vtxs_.end(); ++it, ++n) {
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const instr_fetch_vtx_t& vtx = *it;
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DXGI_FORMAT vtx_format;
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switch (vtx.format) {
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case FMT_1_REVERSE:
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vtx_format = DXGI_FORMAT_R1_UNORM; // ?
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break;
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case FMT_8:
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if (!vtx.num_format_all) {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R8_SNORM : DXGI_FORMAT_R8_UNORM;
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} else {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R8_SINT : DXGI_FORMAT_R8_UINT;
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}
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break;
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case FMT_8_8_8_8:
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if (!vtx.num_format_all) {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R8G8B8A8_SNORM : DXGI_FORMAT_R8G8B8A8_UNORM;
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} else {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R8G8B8A8_SINT : DXGI_FORMAT_R8G8B8A8_UINT;
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}
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break;
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case FMT_2_10_10_10:
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if (!vtx.num_format_all) {
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vtx_format = DXGI_FORMAT_R10G10B10A2_UNORM;
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} else {
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vtx_format = DXGI_FORMAT_R10G10B10A2_UINT;
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}
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break;
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case FMT_8_8:
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if (!vtx.num_format_all) {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R8G8_SNORM : DXGI_FORMAT_R8G8_UNORM;
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} else {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R8G8_SINT : DXGI_FORMAT_R8G8_UINT;
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}
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break;
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case FMT_16:
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if (!vtx.num_format_all) {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R16_SNORM : DXGI_FORMAT_R16_UNORM;
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} else {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R16_SINT : DXGI_FORMAT_R16_UINT;
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}
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break;
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case FMT_16_16:
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if (!vtx.num_format_all) {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R16G16_SNORM : DXGI_FORMAT_R16G16_UNORM;
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} else {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R16G16_SINT : DXGI_FORMAT_R16G16_UINT;
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}
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break;
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case FMT_16_16_16_16:
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if (!vtx.num_format_all) {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R16G16B16A16_SNORM : DXGI_FORMAT_R16G16B16A16_UNORM;
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} else {
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R16G16B16A16_SINT : DXGI_FORMAT_R16G16B16A16_UINT;
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}
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break;
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case FMT_32:
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R32_SINT : DXGI_FORMAT_R32_UINT;
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break;
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case FMT_32_32:
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R32G32_SINT : DXGI_FORMAT_R32G32_UINT;
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break;
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case FMT_32_32_32_32:
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vtx_format = vtx.format_comp_all ?
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DXGI_FORMAT_R32G32B32A32_SINT : DXGI_FORMAT_R32G32B32A32_UINT;
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break;
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case FMT_32_FLOAT:
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vtx_format = DXGI_FORMAT_R32_FLOAT;
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break;
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case FMT_32_32_FLOAT:
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vtx_format = DXGI_FORMAT_R32G32_FLOAT;
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break;
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case FMT_32_32_32_32_FLOAT:
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vtx_format = DXGI_FORMAT_R32G32B32A32_FLOAT;
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break;
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case FMT_32_32_32_FLOAT:
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vtx_format = DXGI_FORMAT_R32G32B32_FLOAT;
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break;
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default:
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XEASSERTALWAYS();
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break;
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}
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element_descs[n].SemanticName = "XE_VF";
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element_descs[n].SemanticIndex = n;
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element_descs[n].Format = vtx_format;
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// Pick slot in same way that driver does.
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// CONST(31, 2) = reg 31, index 2 = rf([31] * 6 + [2] * 2)
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uint32_t fetch_slot = vtx.const_index * 3 + vtx.const_index_sel;
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uint32_t vb_slot = 95 - fetch_slot;
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element_descs[n].InputSlot = vb_slot;
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element_descs[n].AlignedByteOffset = vtx.offset * 4;
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element_descs[n].InputSlotClass = D3D11_INPUT_PER_VERTEX_DATA;
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element_descs[n].InstanceDataStepRate = 0;
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}
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hr = device_->CreateInputLayout(
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element_descs,
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(UINT)element_count,
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byte_code, byte_code_length,
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&input_layout_);
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if (FAILED(hr)) {
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XELOGE("D3D11: failed to create vertex shader input layout");
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xe_free(byte_code);
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return 1;
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}
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xe_free(byte_code);
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is_prepared_ = true;
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return 0;
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}
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const char* D3D11VertexShader::Translate(xe_gpu_program_cntl_t* program_cntl) {
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Output* output = new Output();
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xe_gpu_translate_ctx_t ctx;
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ctx.output = output;
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ctx.type = type_;
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// Add constants buffers.
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// We could optimize this by only including used buffers, but the compiler
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// seems to do a good job of doing this for us.
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// It also does read detection, so c[512] can end up c[4] in the asm -
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// instead of doing this optimization ourselves we could maybe just query
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// this from the compiler.
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output->append(
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"cbuffer float_consts : register(b0) {\n"
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" float4 c[512];\n"
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"};\n");
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// TODO(benvanik): add bool/loop constants.
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// Add vertex shader input.
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output->append(
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"struct VS_INPUT {\n");
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int n = 0;
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for (std::vector<instr_fetch_vtx_t>::iterator it = fetch_vtxs_.begin();
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it != fetch_vtxs_.end(); ++it, ++n) {
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const instr_fetch_vtx_t& vtx = *it;
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uint32_t fetch_slot = vtx.const_index * 3 + vtx.const_index_sel;
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output->append(
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" float4 vf%u_%d : XE_VF%u;\n", fetch_slot, vtx.offset, n);
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}
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output->append(
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"};\n");
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// Add vertex shader output (pixel shader input).
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output->append(
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"struct VS_OUTPUT {\n");
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if (alloc_counts_.positions) {
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XEASSERT(alloc_counts_.positions == 1);
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output->append(
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" float4 oPos : SV_POSITION;\n");
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}
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if (alloc_counts_.params) {
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output->append(
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" float4 o[%d] : XE_O;\n",
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MAX_INTERPOLATORS);
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}
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output->append(
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"};\n");
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// Vertex shader main() header.
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output->append(
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"VS_OUTPUT main(VS_INPUT i) {\n"
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" VS_OUTPUT o;\n");
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// TODO(benvanik): remove this, if possible (though the compiler may be smart
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// enough to do it for us).
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if (alloc_counts_.params) {
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for (uint32_t n = 0; n < MAX_INTERPOLATORS; n++) {
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output->append(
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" o.o[%d] = float4(0.0, 0.0, 0.0, 0.0);\n", n);
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}
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}
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// Add temporaries for any registers we may use.
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uint32_t temp_regs = program_cntl->vs_regs + program_cntl->ps_regs;
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for (uint32_t n = 0; n <= temp_regs; n++) {
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output->append(
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" float4 r%d = c[%d];\n", n, n);
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}
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output->append(" float4 t;\n");
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// Execute blocks.
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for (std::vector<instr_cf_exec_t>::iterator it = execs_.begin();
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it != execs_.end(); ++it) {
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instr_cf_exec_t& cf = *it;
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// TODO(benvanik): figure out how sequences/jmps/loops/etc work.
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if (TranslateExec(ctx, cf)) {
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delete output;
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return NULL;
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}
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}
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// main footer.
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output->append(
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" return o;\n"
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"};\n");
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set_translated_src(output->buffer);
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delete output;
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return translated_src_;
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}
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D3D11PixelShader::D3D11PixelShader(
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ID3D11Device* device,
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const uint8_t* src_ptr, size_t length,
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uint64_t hash) :
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handle_(0),
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D3D11Shader(device, XE_GPU_SHADER_TYPE_PIXEL,
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src_ptr, length, hash) {
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}
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D3D11PixelShader::~D3D11PixelShader() {
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XESAFERELEASE(handle_);
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}
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int D3D11PixelShader::Prepare(xe_gpu_program_cntl_t* program_cntl,
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D3D11VertexShader* input_shader) {
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if (handle_) {
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return 0;
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}
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// TODO(benvanik): look in file based on hash/etc.
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void* byte_code = NULL;
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size_t byte_code_length = 0;
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// Translate and compile source.
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const char* shader_source = Translate(program_cntl, input_shader);
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if (!shader_source) {
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return 1;
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}
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ID3D10Blob* shader_blob = Compile(shader_source);
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if (!shader_blob) {
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return 1;
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}
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byte_code_length = shader_blob->GetBufferSize();
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byte_code = xe_malloc(byte_code_length);
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xe_copy_struct(
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byte_code, shader_blob->GetBufferPointer(), byte_code_length);
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XESAFERELEASE(shader_blob);
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// Create shader.
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HRESULT hr = device_->CreatePixelShader(
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byte_code, byte_code_length,
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NULL,
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&handle_);
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if (FAILED(hr)) {
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XELOGE("D3D11: failed to create pixel shader");
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xe_free(byte_code);
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return 1;
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}
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xe_free(byte_code);
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is_prepared_ = true;
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return 0;
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}
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const char* D3D11PixelShader::Translate(
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xe_gpu_program_cntl_t* program_cntl, D3D11VertexShader* input_shader) {
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Output* output = new Output();
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xe_gpu_translate_ctx_t ctx;
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ctx.output = output;
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ctx.type = type_;
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// We need an input VS to make decisions here.
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// TODO(benvanik): do we need to pair VS/PS up and store the combination?
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|
// If the same PS is used with different VS that output different amounts
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// (and less than the number of required registers), things may die.
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XEASSERTNOTNULL(input_shader);
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const Shader::alloc_counts_t& input_alloc_counts =
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input_shader->alloc_counts();
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|
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// Add constants buffers.
|
|
// We could optimize this by only including used buffers, but the compiler
|
|
// seems to do a good job of doing this for us.
|
|
// It also does read detection, so c[512] can end up c[4] in the asm -
|
|
// instead of doing this optimization ourselves we could maybe just query
|
|
// this from the compiler.
|
|
output->append(
|
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"cbuffer float_consts : register(b0) {\n"
|
|
" float4 c[512];\n"
|
|
"};\n");
|
|
// TODO(benvanik): add bool/loop constants.
|
|
|
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// Add vertex shader output (pixel shader input).
|
|
output->append(
|
|
"struct VS_OUTPUT {\n");
|
|
if (input_alloc_counts.positions) {
|
|
XEASSERT(input_alloc_counts.positions == 1);
|
|
output->append(
|
|
" float4 oPos : SV_POSITION;\n");
|
|
}
|
|
if (input_alloc_counts.params) {
|
|
output->append(
|
|
" float4 o[%d] : XE_O;\n",
|
|
MAX_INTERPOLATORS);
|
|
}
|
|
output->append(
|
|
"};\n");
|
|
|
|
// Add pixel shader output.
|
|
output->append(
|
|
"struct PS_OUTPUT {\n");
|
|
for (uint32_t n = 0; n < alloc_counts_.params; n++) {
|
|
output->append(
|
|
" float4 oC%d : SV_TARGET%d;\n", n, n);
|
|
if (program_cntl->ps_export_depth) {
|
|
// Is this per render-target?
|
|
output->append(
|
|
" float oD%d : SV_DEPTH%d;\n", n, n);
|
|
}
|
|
}
|
|
output->append(
|
|
"};\n");
|
|
|
|
// Pixel shader main() header.
|
|
output->append(
|
|
"PS_OUTPUT main(VS_OUTPUT i) {\n"
|
|
" PS_OUTPUT o;\n");
|
|
|
|
// Add temporary registers.
|
|
uint32_t temp_regs = program_cntl->vs_regs + program_cntl->ps_regs;
|
|
for (uint32_t n = 0; n <= MAX(15, temp_regs); n++) {
|
|
output->append(
|
|
" float4 r%d = c[%d];\n", n, n);
|
|
}
|
|
output->append(" float4 t;\n");
|
|
|
|
// Bring registers local.
|
|
if (input_alloc_counts.params) {
|
|
for (uint32_t n = 0; n < MAX_INTERPOLATORS; n++) {
|
|
output->append(
|
|
" r%d = i.o[%d];\n", n, n);
|
|
}
|
|
}
|
|
|
|
// Execute blocks.
|
|
for (std::vector<instr_cf_exec_t>::iterator it = execs_.begin();
|
|
it != execs_.end(); ++it) {
|
|
instr_cf_exec_t& cf = *it;
|
|
// TODO(benvanik): figure out how sequences/jmps/loops/etc work.
|
|
if (TranslateExec(ctx, cf)) {
|
|
delete output;
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
// main footer.
|
|
output->append(
|
|
" return o;\n"
|
|
"}\n");
|
|
|
|
set_translated_src(output->buffer);
|
|
delete output;
|
|
return translated_src_;
|
|
}
|
|
|
|
|
|
namespace {
|
|
|
|
static const char chan_names[] = {
|
|
'x', 'y', 'z', 'w'
|
|
};
|
|
|
|
void AppendSrcReg(
|
|
xe_gpu_translate_ctx_t& ctx,
|
|
uint32_t num, uint32_t type,
|
|
uint32_t swiz, uint32_t negate, uint32_t abs) {
|
|
if (negate) {
|
|
ctx.output->append("-");
|
|
}
|
|
if (abs) {
|
|
ctx.output->append("abs(");
|
|
}
|
|
if (type) {
|
|
// Register.
|
|
ctx.output->append("r%u", num);
|
|
} else {
|
|
// Constant.
|
|
ctx.output->append("c[%u]", num);
|
|
}
|
|
if (swiz) {
|
|
ctx.output->append(".");
|
|
for (int i = 0; i < 4; i++) {
|
|
ctx.output->append("%c", chan_names[(swiz + i) & 0x3]);
|
|
swiz >>= 2;
|
|
}
|
|
}
|
|
if (abs) {
|
|
ctx.output->append(")");
|
|
}
|
|
}
|
|
|
|
void AppendDestRegName(
|
|
xe_gpu_translate_ctx_t& ctx,
|
|
uint32_t num, uint32_t dst_exp) {
|
|
if (!dst_exp) {
|
|
// Register.
|
|
ctx.output->append("r%u", num);
|
|
} else {
|
|
// Export.
|
|
switch (ctx.type) {
|
|
case XE_GPU_SHADER_TYPE_VERTEX:
|
|
switch (num) {
|
|
case 62:
|
|
ctx.output->append("o.oPos");
|
|
break;
|
|
case 63:
|
|
ctx.output->append("o.point_size");
|
|
break;
|
|
default:
|
|
// Varying.
|
|
ctx.output->append("o.o[%u]", num);;
|
|
break;
|
|
}
|
|
break;
|
|
case XE_GPU_SHADER_TYPE_PIXEL:
|
|
switch (num) {
|
|
case 0:
|
|
ctx.output->append("o.oC0");
|
|
break;
|
|
default:
|
|
// TODO(benvanik): other render targets?
|
|
// TODO(benvanik): depth?
|
|
XEASSERTALWAYS();
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void AppendDestReg(
|
|
xe_gpu_translate_ctx_t& ctx,
|
|
uint32_t num, uint32_t mask, uint32_t dst_exp) {
|
|
if (mask != 0xF) {
|
|
// If masking, store to a temporary variable and clean it up later.
|
|
ctx.output->append("t");
|
|
} else {
|
|
// Store directly to output.
|
|
AppendDestRegName(ctx, num, dst_exp);
|
|
}
|
|
}
|
|
|
|
void AppendDestRegPost(
|
|
xe_gpu_translate_ctx_t& ctx,
|
|
uint32_t num, uint32_t mask, uint32_t dst_exp) {
|
|
if (mask != 0xF) {
|
|
// Masking.
|
|
ctx.output->append(" ");
|
|
AppendDestRegName(ctx, num, dst_exp);
|
|
ctx.output->append(" = float4(");
|
|
for (int i = 0; i < 4; i++) {
|
|
// TODO(benvanik): mask out values? mix in old value as temp?
|
|
// ctx.output->append("%c", (mask & 0x1) ? chan_names[i] : 'w');
|
|
if (!(mask & 0x1)) {
|
|
AppendDestRegName(ctx, num, dst_exp);
|
|
} else {
|
|
ctx.output->append("t");
|
|
}
|
|
ctx.output->append(".%c", chan_names[i]);
|
|
mask >>= 1;
|
|
if (i < 3) {
|
|
ctx.output->append(", ");
|
|
}
|
|
}
|
|
ctx.output->append(");\n");
|
|
}
|
|
}
|
|
|
|
void print_srcreg(
|
|
Output* output,
|
|
uint32_t num, uint32_t type,
|
|
uint32_t swiz, uint32_t negate, uint32_t abs) {
|
|
if (negate) {
|
|
output->append("-");
|
|
}
|
|
if (abs) {
|
|
output->append("|");
|
|
}
|
|
output->append("%c%u", type ? 'R' : 'C', num);
|
|
if (swiz) {
|
|
output->append(".");
|
|
for (int i = 0; i < 4; i++) {
|
|
output->append("%c", chan_names[(swiz + i) & 0x3]);
|
|
swiz >>= 2;
|
|
}
|
|
}
|
|
if (abs) {
|
|
output->append("|");
|
|
}
|
|
}
|
|
|
|
void print_dstreg(
|
|
Output* output, uint32_t num, uint32_t mask, uint32_t dst_exp) {
|
|
output->append("%s%u", dst_exp ? "export" : "R", num);
|
|
if (mask != 0xf) {
|
|
output->append(".");
|
|
for (int i = 0; i < 4; i++) {
|
|
output->append("%c", (mask & 0x1) ? chan_names[i] : '_');
|
|
mask >>= 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
void print_export_comment(
|
|
Output* output, uint32_t num, XE_GPU_SHADER_TYPE type) {
|
|
const char *name = NULL;
|
|
switch (type) {
|
|
case XE_GPU_SHADER_TYPE_VERTEX:
|
|
switch (num) {
|
|
case 62: name = "gl_Position"; break;
|
|
case 63: name = "gl_PointSize"; break;
|
|
}
|
|
break;
|
|
case XE_GPU_SHADER_TYPE_PIXEL:
|
|
switch (num) {
|
|
case 0: name = "gl_FragColor"; break;
|
|
}
|
|
break;
|
|
}
|
|
/* if we had a symbol table here, we could look
|
|
* up the name of the varying..
|
|
*/
|
|
if (name) {
|
|
output->append("\t; %s", name);
|
|
}
|
|
}
|
|
|
|
int TranslateALU_ADDv(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
|
|
AppendDestReg(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
ctx.output->append(" = ");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append("saturate(");
|
|
}
|
|
ctx.output->append("(");
|
|
AppendSrcReg(ctx, alu.src1_reg, alu.src1_sel, alu.src1_swiz, alu.src1_reg_negate, alu.src1_reg_abs);
|
|
ctx.output->append(" + ");
|
|
AppendSrcReg(ctx, alu.src2_reg, alu.src2_sel, alu.src2_swiz, alu.src2_reg_negate, alu.src2_reg_abs);
|
|
ctx.output->append(")");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append(")");
|
|
}
|
|
ctx.output->append(";\n");
|
|
AppendDestRegPost(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
return 0;
|
|
}
|
|
|
|
int TranslateALU_MULv(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
|
|
AppendDestReg(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
ctx.output->append(" = ");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append("saturate(");
|
|
}
|
|
ctx.output->append("(");
|
|
AppendSrcReg(ctx, alu.src1_reg, alu.src1_sel, alu.src1_swiz, alu.src1_reg_negate, alu.src1_reg_abs);
|
|
ctx.output->append(" * ");
|
|
AppendSrcReg(ctx, alu.src2_reg, alu.src2_sel, alu.src2_swiz, alu.src2_reg_negate, alu.src2_reg_abs);
|
|
ctx.output->append(")");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append(")");
|
|
}
|
|
ctx.output->append(";\n");
|
|
AppendDestRegPost(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
return 0;
|
|
}
|
|
|
|
int TranslateALU_MAXv(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
|
|
AppendDestReg(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
ctx.output->append(" = ");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append("saturate(");
|
|
}
|
|
if (alu.src1_reg == alu.src2_reg &&
|
|
alu.src1_sel == alu.src2_sel &&
|
|
alu.src1_swiz == alu.src2_swiz &&
|
|
alu.src1_reg_negate == alu.src2_reg_negate &&
|
|
alu.src1_reg_abs == alu.src2_reg_abs) {
|
|
// This is a mov.
|
|
AppendSrcReg(ctx, alu.src1_reg, alu.src1_sel, alu.src1_swiz, alu.src1_reg_negate, alu.src1_reg_abs);
|
|
} else {
|
|
ctx.output->append("max(");
|
|
AppendSrcReg(ctx, alu.src1_reg, alu.src1_sel, alu.src1_swiz, alu.src1_reg_negate, alu.src1_reg_abs);
|
|
ctx.output->append(", ");
|
|
AppendSrcReg(ctx, alu.src2_reg, alu.src2_sel, alu.src2_swiz, alu.src2_reg_negate, alu.src2_reg_abs);
|
|
ctx.output->append(")");
|
|
}
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append(")");
|
|
}
|
|
ctx.output->append(";\n");
|
|
AppendDestRegPost(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
return 0;
|
|
}
|
|
|
|
int TranslateALU_MINv(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
|
|
AppendDestReg(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
ctx.output->append(" = ");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append("saturate(");
|
|
}
|
|
ctx.output->append("min(");
|
|
AppendSrcReg(ctx, alu.src1_reg, alu.src1_sel, alu.src1_swiz, alu.src1_reg_negate, alu.src1_reg_abs);
|
|
ctx.output->append(", ");
|
|
AppendSrcReg(ctx, alu.src2_reg, alu.src2_sel, alu.src2_swiz, alu.src2_reg_negate, alu.src2_reg_abs);
|
|
ctx.output->append(")");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append(")");
|
|
}
|
|
ctx.output->append(";\n");
|
|
AppendDestRegPost(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
return 0;
|
|
}
|
|
|
|
int TranslateALU_FRACv(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
|
|
AppendDestReg(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
ctx.output->append(" = ");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append("saturate(");
|
|
}
|
|
ctx.output->append("frac(");
|
|
AppendSrcReg(ctx, alu.src1_reg, alu.src1_sel, alu.src1_swiz, alu.src1_reg_negate, alu.src1_reg_abs);
|
|
ctx.output->append(")");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append(")");
|
|
}
|
|
ctx.output->append(";\n");
|
|
AppendDestRegPost(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
return 0;
|
|
}
|
|
|
|
int TranslateALU_TRUNCv(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
|
|
AppendDestReg(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
ctx.output->append(" = ");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append("saturate(");
|
|
}
|
|
ctx.output->append("trunc(");
|
|
AppendSrcReg(ctx, alu.src1_reg, alu.src1_sel, alu.src1_swiz, alu.src1_reg_negate, alu.src1_reg_abs);
|
|
ctx.output->append(")");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append(")");
|
|
}
|
|
ctx.output->append(";\n");
|
|
AppendDestRegPost(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
return 0;
|
|
}
|
|
|
|
int TranslateALU_FLOORv(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
|
|
AppendDestReg(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
ctx.output->append(" = ");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append("saturate(");
|
|
}
|
|
ctx.output->append("floor(");
|
|
AppendSrcReg(ctx, alu.src1_reg, alu.src1_sel, alu.src1_swiz, alu.src1_reg_negate, alu.src1_reg_abs);
|
|
ctx.output->append(")");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append(")");
|
|
}
|
|
ctx.output->append(";\n");
|
|
AppendDestRegPost(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
return 0;
|
|
}
|
|
|
|
// ...
|
|
|
|
int TranslateALU_MULADDv(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
|
|
AppendDestReg(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
ctx.output->append(" = ");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append("saturate(");
|
|
}
|
|
ctx.output->append("mad(");
|
|
AppendSrcReg(ctx, alu.src2_reg, alu.src2_sel, alu.src2_swiz, alu.src2_reg_negate, alu.src2_reg_abs);
|
|
ctx.output->append(", ");
|
|
AppendSrcReg(ctx, alu.src3_reg, alu.src3_sel, alu.src3_swiz, alu.src3_reg_negate, alu.src3_reg_abs);
|
|
ctx.output->append(", ");
|
|
AppendSrcReg(ctx, alu.src1_reg, alu.src1_sel, alu.src1_swiz, alu.src1_reg_negate, alu.src1_reg_abs);
|
|
ctx.output->append(")");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append(")");
|
|
}
|
|
ctx.output->append(";\n");
|
|
AppendDestRegPost(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
return 0;
|
|
}
|
|
|
|
int TranslateALU_DOT4v(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
|
|
AppendDestReg(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
ctx.output->append(" = ");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append("saturate(");
|
|
}
|
|
ctx.output->append("dot(");
|
|
AppendSrcReg(ctx, alu.src1_reg, alu.src1_sel, alu.src1_swiz, alu.src1_reg_negate, alu.src1_reg_abs);
|
|
ctx.output->append(", ");
|
|
AppendSrcReg(ctx, alu.src2_reg, alu.src2_sel, alu.src2_swiz, alu.src2_reg_negate, alu.src2_reg_abs);
|
|
ctx.output->append(")");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append(")");
|
|
}
|
|
ctx.output->append(";\n");
|
|
AppendDestRegPost(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
return 0;
|
|
}
|
|
|
|
int TranslateALU_DOT3v(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
|
|
AppendDestReg(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
ctx.output->append(" = ");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append("saturate(");
|
|
}
|
|
ctx.output->append("dot(float4(");
|
|
AppendSrcReg(ctx, alu.src1_reg, alu.src1_sel, alu.src1_swiz, alu.src1_reg_negate, alu.src1_reg_abs);
|
|
ctx.output->append(").xyz, float4(");
|
|
AppendSrcReg(ctx, alu.src2_reg, alu.src2_sel, alu.src2_swiz, alu.src2_reg_negate, alu.src2_reg_abs);
|
|
ctx.output->append(").xyz)");
|
|
if (alu.vector_clamp) {
|
|
ctx.output->append(")");
|
|
}
|
|
ctx.output->append(";\n");
|
|
AppendDestRegPost(ctx, alu.vector_dest, alu.vector_write_mask, alu.export_data);
|
|
return 0;
|
|
}
|
|
|
|
typedef int (*xe_gpu_translate_alu_fn)(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu);
|
|
typedef struct {
|
|
uint32_t num_srcs;
|
|
const char* name;
|
|
xe_gpu_translate_alu_fn fn;
|
|
} xe_gpu_translate_alu_info_t;
|
|
#define ALU_INSTR(opc, num_srcs) \
|
|
{ num_srcs, #opc, 0 }
|
|
#define ALU_INSTR_IMPL(opc, num_srcs) \
|
|
{ num_srcs, #opc, TranslateALU_##opc }
|
|
static xe_gpu_translate_alu_info_t vector_alu_instrs[0x20] = {
|
|
ALU_INSTR_IMPL(ADDv, 2), // 0
|
|
ALU_INSTR_IMPL(MULv, 2), // 1
|
|
ALU_INSTR_IMPL(MAXv, 2), // 2
|
|
ALU_INSTR_IMPL(MINv, 2), // 3
|
|
ALU_INSTR(SETEv, 2), // 4
|
|
ALU_INSTR(SETGTv, 2), // 5
|
|
ALU_INSTR(SETGTEv, 2), // 6
|
|
ALU_INSTR(SETNEv, 2), // 7
|
|
ALU_INSTR_IMPL(FRACv, 1), // 8
|
|
ALU_INSTR_IMPL(TRUNCv, 1), // 9
|
|
ALU_INSTR_IMPL(FLOORv, 1), // 10
|
|
ALU_INSTR_IMPL(MULADDv, 3), // 11
|
|
ALU_INSTR(CNDEv, 3), // 12
|
|
ALU_INSTR(CNDGTEv, 3), // 13
|
|
ALU_INSTR(CNDGTv, 3), // 14
|
|
ALU_INSTR_IMPL(DOT4v, 2), // 15
|
|
ALU_INSTR_IMPL(DOT3v, 2), // 16
|
|
ALU_INSTR(DOT2ADDv, 3), // 17 -- ???
|
|
ALU_INSTR(CUBEv, 2), // 18
|
|
ALU_INSTR(MAX4v, 1), // 19
|
|
ALU_INSTR(PRED_SETE_PUSHv, 2), // 20
|
|
ALU_INSTR(PRED_SETNE_PUSHv, 2), // 21
|
|
ALU_INSTR(PRED_SETGT_PUSHv, 2), // 22
|
|
ALU_INSTR(PRED_SETGTE_PUSHv, 2), // 23
|
|
ALU_INSTR(KILLEv, 2), // 24
|
|
ALU_INSTR(KILLGTv, 2), // 25
|
|
ALU_INSTR(KILLGTEv, 2), // 26
|
|
ALU_INSTR(KILLNEv, 2), // 27
|
|
ALU_INSTR(DSTv, 2), // 28
|
|
ALU_INSTR(MOVAv, 1), // 29
|
|
};
|
|
static xe_gpu_translate_alu_info_t scalar_alu_instrs[0x40] = {
|
|
ALU_INSTR(ADDs, 1), // 0
|
|
ALU_INSTR(ADD_PREVs, 1), // 1
|
|
ALU_INSTR(MULs, 1), // 2
|
|
ALU_INSTR(MUL_PREVs, 1), // 3
|
|
ALU_INSTR(MUL_PREV2s, 1), // 4
|
|
ALU_INSTR(MAXs, 1), // 5
|
|
ALU_INSTR(MINs, 1), // 6
|
|
ALU_INSTR(SETEs, 1), // 7
|
|
ALU_INSTR(SETGTs, 1), // 8
|
|
ALU_INSTR(SETGTEs, 1), // 9
|
|
ALU_INSTR(SETNEs, 1), // 10
|
|
ALU_INSTR(FRACs, 1), // 11
|
|
ALU_INSTR(TRUNCs, 1), // 12
|
|
ALU_INSTR(FLOORs, 1), // 13
|
|
ALU_INSTR(EXP_IEEE, 1), // 14
|
|
ALU_INSTR(LOG_CLAMP, 1), // 15
|
|
ALU_INSTR(LOG_IEEE, 1), // 16
|
|
ALU_INSTR(RECIP_CLAMP, 1), // 17
|
|
ALU_INSTR(RECIP_FF, 1), // 18
|
|
ALU_INSTR(RECIP_IEEE, 1), // 19
|
|
ALU_INSTR(RECIPSQ_CLAMP, 1), // 20
|
|
ALU_INSTR(RECIPSQ_FF, 1), // 21
|
|
ALU_INSTR(RECIPSQ_IEEE, 1), // 22
|
|
ALU_INSTR(MOVAs, 1), // 23
|
|
ALU_INSTR(MOVA_FLOORs, 1), // 24
|
|
ALU_INSTR(SUBs, 1), // 25
|
|
ALU_INSTR(SUB_PREVs, 1), // 26
|
|
ALU_INSTR(PRED_SETEs, 1), // 27
|
|
ALU_INSTR(PRED_SETNEs, 1), // 28
|
|
ALU_INSTR(PRED_SETGTs, 1), // 29
|
|
ALU_INSTR(PRED_SETGTEs, 1), // 30
|
|
ALU_INSTR(PRED_SET_INVs, 1), // 31
|
|
ALU_INSTR(PRED_SET_POPs, 1), // 32
|
|
ALU_INSTR(PRED_SET_CLRs, 1), // 33
|
|
ALU_INSTR(PRED_SET_RESTOREs, 1), // 34
|
|
ALU_INSTR(KILLEs, 1), // 35
|
|
ALU_INSTR(KILLGTs, 1), // 36
|
|
ALU_INSTR(KILLGTEs, 1), // 37
|
|
ALU_INSTR(KILLNEs, 1), // 38
|
|
ALU_INSTR(KILLONEs, 1), // 39
|
|
ALU_INSTR(SQRT_IEEE, 1), // 40
|
|
{ 0, 0, false },
|
|
ALU_INSTR(MUL_CONST_0, 2), // 42
|
|
ALU_INSTR(MUL_CONST_1, 2), // 43
|
|
ALU_INSTR(ADD_CONST_0, 2), // 44
|
|
ALU_INSTR(ADD_CONST_1, 2), // 45
|
|
ALU_INSTR(SUB_CONST_0, 2), // 46
|
|
ALU_INSTR(SUB_CONST_1, 2), // 47
|
|
ALU_INSTR(SIN, 1), // 48
|
|
ALU_INSTR(COS, 1), // 49
|
|
ALU_INSTR(RETAIN_PREV, 1), // 50
|
|
};
|
|
#undef ALU_INSTR
|
|
|
|
int TranslateALU(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_alu_t* alu, int sync) {
|
|
Output* output = ctx.output;
|
|
|
|
if (!alu->scalar_write_mask && !alu->vector_write_mask) {
|
|
output->append(" // <nop>\n");
|
|
return 0;
|
|
}
|
|
|
|
if (alu->vector_write_mask) {
|
|
// Disassemble vector op.
|
|
xe_gpu_translate_alu_info_t& iv = vector_alu_instrs[alu->vector_opc];
|
|
output->append(" // %sALU:\t", sync ? "(S)" : " ");
|
|
output->append("%s", iv.name);
|
|
if (alu->pred_select & 0x2) {
|
|
// seems to work similar to conditional execution in ARM instruction
|
|
// set, so let's use a similar syntax for now:
|
|
output->append((alu->pred_select & 0x1) ? "EQ" : "NE");
|
|
}
|
|
output->append("\t");
|
|
print_dstreg(output,
|
|
alu->vector_dest, alu->vector_write_mask, alu->export_data);
|
|
output->append(" = ");
|
|
if (iv.num_srcs == 3) {
|
|
print_srcreg(output,
|
|
alu->src3_reg, alu->src3_sel, alu->src3_swiz,
|
|
alu->src3_reg_negate, alu->src3_reg_abs);
|
|
output->append(", ");
|
|
}
|
|
print_srcreg(output,
|
|
alu->src1_reg, alu->src1_sel, alu->src1_swiz,
|
|
alu->src1_reg_negate, alu->src1_reg_abs);
|
|
if (iv.num_srcs > 1) {
|
|
output->append(", ");
|
|
print_srcreg(output,
|
|
alu->src2_reg, alu->src2_sel, alu->src2_swiz,
|
|
alu->src2_reg_negate, alu->src2_reg_abs);
|
|
}
|
|
if (alu->vector_clamp) {
|
|
output->append(" CLAMP");
|
|
}
|
|
if (alu->export_data) {
|
|
print_export_comment(output, alu->vector_dest, ctx.type);
|
|
}
|
|
output->append("\n");
|
|
|
|
// Translate vector op.
|
|
if (iv.fn) {
|
|
output->append(" ");
|
|
if (iv.fn(ctx, *alu)) {
|
|
return 1;
|
|
}
|
|
} else {
|
|
output->append(" // <UNIMPLEMENTED>\n");
|
|
}
|
|
}
|
|
|
|
if (alu->scalar_write_mask || !alu->vector_write_mask) {
|
|
// 2nd optional scalar op:
|
|
|
|
// Disassemble scalar op.
|
|
xe_gpu_translate_alu_info_t& is = scalar_alu_instrs[alu->scalar_opc];
|
|
output->append(" // ");
|
|
output->append("\t");
|
|
if (is.name) {
|
|
output->append("\t \t%s\t", is.name);
|
|
} else {
|
|
output->append("\t \tOP(%u)\t", alu->scalar_opc);
|
|
}
|
|
print_dstreg(output,
|
|
alu->scalar_dest, alu->scalar_write_mask, alu->export_data);
|
|
output->append(" = ");
|
|
print_srcreg(output,
|
|
alu->src3_reg, alu->src3_sel, alu->src3_swiz,
|
|
alu->src3_reg_negate, alu->src3_reg_abs);
|
|
// TODO ADD/MUL must have another src?!?
|
|
if (alu->scalar_clamp) {
|
|
output->append(" CLAMP");
|
|
}
|
|
if (alu->export_data) {
|
|
print_export_comment(output, alu->scalar_dest, ctx.type);
|
|
}
|
|
output->append("\n");
|
|
|
|
// Translate scalar op.
|
|
if (is.fn) {
|
|
output->append(" ");
|
|
if (is.fn(ctx, *alu)) {
|
|
return 1;
|
|
}
|
|
} else {
|
|
output->append(" // <UNIMPLEMENTED>\n");
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct {
|
|
const char *name;
|
|
} fetch_types[0xff] = {
|
|
#define TYPE(id) { #id }
|
|
TYPE(FMT_1_REVERSE), // 0
|
|
{0},
|
|
TYPE(FMT_8), // 2
|
|
{0},
|
|
{0},
|
|
{0},
|
|
TYPE(FMT_8_8_8_8), // 6
|
|
TYPE(FMT_2_10_10_10), // 7
|
|
{0},
|
|
{0},
|
|
TYPE(FMT_8_8), // 10
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
TYPE(FMT_16), // 24
|
|
TYPE(FMT_16_16), // 25
|
|
TYPE(FMT_16_16_16_16), // 26
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
TYPE(FMT_32), // 33
|
|
TYPE(FMT_32_32), // 34
|
|
TYPE(FMT_32_32_32_32), // 35
|
|
TYPE(FMT_32_FLOAT), // 36
|
|
TYPE(FMT_32_32_FLOAT), // 37
|
|
TYPE(FMT_32_32_32_32_FLOAT), // 38
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
TYPE(FMT_32_32_32_FLOAT), // 57
|
|
#undef TYPE
|
|
};
|
|
|
|
void print_fetch_dst(Output* output, uint32_t dst_reg, uint32_t dst_swiz) {
|
|
output->append("\tR%u.", dst_reg);
|
|
for (int i = 0; i < 4; i++) {
|
|
output->append("%c", chan_names[dst_swiz & 0x7]);
|
|
dst_swiz >>= 3;
|
|
}
|
|
}
|
|
|
|
void AppendFetchDest(Output* output, uint32_t dst_reg, uint32_t dst_swiz) {
|
|
output->append("r%u.", dst_reg);
|
|
for (int i = 0; i < 4; i++) {
|
|
output->append("%c", chan_names[dst_swiz & 0x7]);
|
|
dst_swiz >>= 3;
|
|
}
|
|
}
|
|
|
|
int TranslateVertexFetch(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_fetch_vtx_t* vtx, int sync) {
|
|
Output* output = ctx.output;
|
|
|
|
// Disassemble.
|
|
output->append(" // %sFETCH:\t", sync ? "(S)" : " ");
|
|
if (vtx->pred_select) {
|
|
output->append(vtx->pred_condition ? "EQ" : "NE");
|
|
}
|
|
print_fetch_dst(output, vtx->dst_reg, vtx->dst_swiz);
|
|
output->append(" = R%u.", vtx->src_reg);
|
|
output->append("%c", chan_names[vtx->src_swiz & 0x3]);
|
|
if (fetch_types[vtx->format].name) {
|
|
output->append(" %s", fetch_types[vtx->format].name);
|
|
} else {
|
|
output->append(" TYPE(0x%x)", vtx->format);
|
|
}
|
|
output->append(" %s", vtx->format_comp_all ? "SIGNED" : "UNSIGNED");
|
|
if (!vtx->num_format_all) {
|
|
output->append(" NORMALIZED");
|
|
}
|
|
output->append(" STRIDE(%u)", vtx->stride);
|
|
if (vtx->offset) {
|
|
output->append(" OFFSET(%u)", vtx->offset);
|
|
}
|
|
output->append(" CONST(%u, %u)", vtx->const_index, vtx->const_index_sel);
|
|
if (1) {
|
|
// XXX
|
|
output->append(" src_reg_am=%u", vtx->src_reg_am);
|
|
output->append(" dst_reg_am=%u", vtx->dst_reg_am);
|
|
output->append(" num_format_all=%u", vtx->num_format_all);
|
|
output->append(" signed_rf_mode_all=%u", vtx->signed_rf_mode_all);
|
|
output->append(" exp_adjust_all=%u", vtx->exp_adjust_all);
|
|
}
|
|
output->append("\n");
|
|
|
|
// Translate.
|
|
output->append(" ");
|
|
output->append("r%u.xyzw", vtx->dst_reg);
|
|
output->append(" = ");
|
|
uint32_t fetch_slot = vtx->const_index * 3 + vtx->const_index_sel;
|
|
output->append("i.vf%u_%d.", fetch_slot, vtx->offset);
|
|
// Pass one over dest does xyzw and fakes the special values.
|
|
// TODO(benvanik): detect and set as rN = float4(samp.xyz, 1.0); / etc
|
|
uint32_t dst_swiz = vtx->dst_swiz;
|
|
for (int i = 0; i < 4; i++) {
|
|
output->append("%c", chan_names[dst_swiz & 0x3]);
|
|
dst_swiz >>= 3;
|
|
}
|
|
output->append(";\n");
|
|
// Do another pass to set constant values.
|
|
dst_swiz = vtx->dst_swiz;
|
|
for (int i = 0; i < 4; i++) {
|
|
if ((dst_swiz & 0x7) == 4) {
|
|
output->append(" r%u.%c = 0.0;\n", vtx->dst_reg, chan_names[i]);
|
|
} else if ((dst_swiz & 0x7) == 5) {
|
|
output->append(" r%u.%c = 1.0;\n", vtx->dst_reg, chan_names[i]);
|
|
}
|
|
dst_swiz >>= 3;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int TranslateTextureFetch(
|
|
xe_gpu_translate_ctx_t& ctx, const instr_fetch_tex_t* tex, int sync) {
|
|
Output* output = ctx.output;
|
|
|
|
// Disassemble.
|
|
static const char *filter[] = {
|
|
"POINT", // TEX_FILTER_POINT
|
|
"LINEAR", // TEX_FILTER_LINEAR
|
|
"BASEMAP", // TEX_FILTER_BASEMAP
|
|
};
|
|
static const char *aniso_filter[] = {
|
|
"DISABLED", // ANISO_FILTER_DISABLED
|
|
"MAX_1_1", // ANISO_FILTER_MAX_1_1
|
|
"MAX_2_1", // ANISO_FILTER_MAX_2_1
|
|
"MAX_4_1", // ANISO_FILTER_MAX_4_1
|
|
"MAX_8_1", // ANISO_FILTER_MAX_8_1
|
|
"MAX_16_1", // ANISO_FILTER_MAX_16_1
|
|
};
|
|
static const char *arbitrary_filter[] = {
|
|
"2x4_SYM", // ARBITRARY_FILTER_2X4_SYM
|
|
"2x4_ASYM", // ARBITRARY_FILTER_2X4_ASYM
|
|
"4x2_SYM", // ARBITRARY_FILTER_4X2_SYM
|
|
"4x2_ASYM", // ARBITRARY_FILTER_4X2_ASYM
|
|
"4x4_SYM", // ARBITRARY_FILTER_4X4_SYM
|
|
"4x4_ASYM", // ARBITRARY_FILTER_4X4_ASYM
|
|
};
|
|
static const char *sample_loc[] = {
|
|
"CENTROID", // SAMPLE_CENTROID
|
|
"CENTER", // SAMPLE_CENTER
|
|
};
|
|
uint32_t src_swiz = tex->src_swiz;
|
|
output->append(" // %sFETCH:\t", sync ? "(S)" : " ");
|
|
if (tex->pred_select) {
|
|
output->append(tex->pred_condition ? "EQ" : "NE");
|
|
}
|
|
print_fetch_dst(output, tex->dst_reg, tex->dst_swiz);
|
|
output->append(" = R%u.", tex->src_reg);
|
|
for (int i = 0; i < 3; i++) {
|
|
output->append("%c", chan_names[src_swiz & 0x3]);
|
|
src_swiz >>= 2;
|
|
}
|
|
output->append(" CONST(%u)", tex->const_idx);
|
|
if (tex->fetch_valid_only) {
|
|
output->append(" VALID_ONLY");
|
|
}
|
|
if (tex->tx_coord_denorm) {
|
|
output->append(" DENORM");
|
|
}
|
|
if (tex->mag_filter != TEX_FILTER_USE_FETCH_CONST) {
|
|
output->append(" MAG(%s)", filter[tex->mag_filter]);
|
|
}
|
|
if (tex->min_filter != TEX_FILTER_USE_FETCH_CONST) {
|
|
output->append(" MIN(%s)", filter[tex->min_filter]);
|
|
}
|
|
if (tex->mip_filter != TEX_FILTER_USE_FETCH_CONST) {
|
|
output->append(" MIP(%s)", filter[tex->mip_filter]);
|
|
}
|
|
if (tex->aniso_filter != ANISO_FILTER_USE_FETCH_CONST) {
|
|
output->append(" ANISO(%s)", aniso_filter[tex->aniso_filter]);
|
|
}
|
|
if (tex->arbitrary_filter != ARBITRARY_FILTER_USE_FETCH_CONST) {
|
|
output->append(" ARBITRARY(%s)", arbitrary_filter[tex->arbitrary_filter]);
|
|
}
|
|
if (tex->vol_mag_filter != TEX_FILTER_USE_FETCH_CONST) {
|
|
output->append(" VOL_MAG(%s)", filter[tex->vol_mag_filter]);
|
|
}
|
|
if (tex->vol_min_filter != TEX_FILTER_USE_FETCH_CONST) {
|
|
output->append(" VOL_MIN(%s)", filter[tex->vol_min_filter]);
|
|
}
|
|
if (!tex->use_comp_lod) {
|
|
output->append(" LOD(%u)", tex->use_comp_lod);
|
|
output->append(" LOD_BIAS(%u)", tex->lod_bias);
|
|
}
|
|
if (tex->use_reg_lod) {
|
|
output->append(" REG_LOD(%u)", tex->use_reg_lod);
|
|
}
|
|
if (tex->use_reg_gradients) {
|
|
output->append(" USE_REG_GRADIENTS");
|
|
}
|
|
output->append(" LOCATION(%s)", sample_loc[tex->sample_location]);
|
|
if (tex->offset_x || tex->offset_y || tex->offset_z) {
|
|
output->append(" OFFSET(%u,%u,%u)", tex->offset_x, tex->offset_y, tex->offset_z);
|
|
}
|
|
output->append("\n");
|
|
|
|
// Translate.
|
|
src_swiz = tex->src_swiz;
|
|
output->append(" ");
|
|
output->append("r%u.xyzw", tex->dst_reg);
|
|
output->append(" = ");
|
|
uint32_t fetch_slot = tex->const_idx * 3;
|
|
//output->append("i.vf%u_%d.", fetch_slot, vtx->offset);
|
|
// Texture2D some_texture;
|
|
// SamplerState some_sampler;
|
|
// some_texture.Sample(some_sampler, coords)
|
|
output->append("float4(1.0, 0.0, 0.0, 1.0).");
|
|
// Pass one over dest does xyzw and fakes the special values.
|
|
// TODO(benvanik): detect and set as rN = float4(samp.xyz, 1.0); / etc
|
|
uint32_t dst_swiz = tex->dst_swiz;
|
|
for (int i = 0; i < 4; i++) {
|
|
output->append("%c", chan_names[dst_swiz & 0x3]);
|
|
dst_swiz >>= 3;
|
|
}
|
|
output->append(";\n");
|
|
// Do another pass to set constant values.
|
|
dst_swiz = tex->dst_swiz;
|
|
for (int i = 0; i < 4; i++) {
|
|
if ((dst_swiz & 0x7) == 4) {
|
|
output->append(" r%u.%c = 0.0;\n", tex->dst_reg, chan_names[i]);
|
|
} else if ((dst_swiz & 0x7) == 5) {
|
|
output->append(" r%u.%c = 1.0;\n", tex->dst_reg, chan_names[i]);
|
|
}
|
|
dst_swiz >>= 3;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
struct {
|
|
const char *name;
|
|
} cf_instructions[] = {
|
|
#define INSTR(opc, fxn) { #opc }
|
|
INSTR(NOP, print_cf_nop),
|
|
INSTR(EXEC, print_cf_exec),
|
|
INSTR(EXEC_END, print_cf_exec),
|
|
INSTR(COND_EXEC, print_cf_exec),
|
|
INSTR(COND_EXEC_END, print_cf_exec),
|
|
INSTR(COND_PRED_EXEC, print_cf_exec),
|
|
INSTR(COND_PRED_EXEC_END, print_cf_exec),
|
|
INSTR(LOOP_START, print_cf_loop),
|
|
INSTR(LOOP_END, print_cf_loop),
|
|
INSTR(COND_CALL, print_cf_jmp_call),
|
|
INSTR(RETURN, print_cf_jmp_call),
|
|
INSTR(COND_JMP, print_cf_jmp_call),
|
|
INSTR(ALLOC, print_cf_alloc),
|
|
INSTR(COND_EXEC_PRED_CLEAN, print_cf_exec),
|
|
INSTR(COND_EXEC_PRED_CLEAN_END, print_cf_exec),
|
|
INSTR(MARK_VS_FETCH_DONE, print_cf_nop), // ??
|
|
#undef INSTR
|
|
};
|
|
|
|
} // anonymous namespace
|
|
|
|
|
|
int D3D11Shader::TranslateExec(xe_gpu_translate_ctx_t& ctx, const instr_cf_exec_t& cf) {
|
|
Output* output = ctx.output;
|
|
|
|
output->append(
|
|
" // %s ADDR(0x%x) CNT(0x%x)",
|
|
cf_instructions[cf.opc].name, cf.address, cf.count);
|
|
if (cf.yeild) {
|
|
output->append(" YIELD");
|
|
}
|
|
uint8_t vc = cf.vc_hi | (cf.vc_lo << 2);
|
|
if (vc) {
|
|
output->append(" VC(0x%x)", vc);
|
|
}
|
|
if (cf.bool_addr) {
|
|
output->append(" BOOL_ADDR(0x%x)", cf.bool_addr);
|
|
}
|
|
if (cf.address_mode == ABSOLUTE_ADDR) {
|
|
output->append(" ABSOLUTE_ADDR");
|
|
}
|
|
if (cf.is_cond_exec()) {
|
|
output->append(" COND(%d)", cf.condition);
|
|
}
|
|
output->append("\n");
|
|
|
|
uint32_t sequence = cf.serialize;
|
|
for (uint32_t i = 0; i < cf.count; i++) {
|
|
uint32_t alu_off = (cf.address + i);
|
|
int sync = sequence & 0x2;
|
|
if (sequence & 0x1) {
|
|
const instr_fetch_t* fetch =
|
|
(const instr_fetch_t*)(dwords_ + alu_off * 3);
|
|
switch (fetch->opc) {
|
|
case VTX_FETCH:
|
|
if (TranslateVertexFetch(ctx, &fetch->vtx, sync)) {
|
|
return 1;
|
|
}
|
|
break;
|
|
case TEX_FETCH:
|
|
if (TranslateTextureFetch(ctx, &fetch->tex, sync)) {
|
|
return 1;
|
|
}
|
|
break;
|
|
case TEX_GET_BORDER_COLOR_FRAC:
|
|
case TEX_GET_COMP_TEX_LOD:
|
|
case TEX_GET_GRADIENTS:
|
|
case TEX_GET_WEIGHTS:
|
|
case TEX_SET_TEX_LOD:
|
|
case TEX_SET_GRADIENTS_H:
|
|
case TEX_SET_GRADIENTS_V:
|
|
default:
|
|
XEASSERTALWAYS();
|
|
break;
|
|
}
|
|
} else {
|
|
const instr_alu_t* alu =
|
|
(const instr_alu_t*)(dwords_ + alu_off * 3);
|
|
if (TranslateALU(ctx, alu, sync)) {
|
|
return 1;
|
|
}
|
|
}
|
|
sequence >>= 2;
|
|
}
|
|
|
|
return 0;
|
|
}
|