120 lines
4.9 KiB
Plaintext
120 lines
4.9 KiB
Plaintext
//
|
|
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
|
|
//
|
|
//
|
|
// Buffer Definitions:
|
|
//
|
|
// cbuffer xe_system_cbuffer
|
|
// {
|
|
//
|
|
// uint xe_flags; // Offset: 0 Size: 4 [unused]
|
|
// uint xe_line_loop_closing_index; // Offset: 4 Size: 4 [unused]
|
|
// uint xe_vertex_index_endian; // Offset: 8 Size: 4 [unused]
|
|
// int xe_vertex_base_index; // Offset: 12 Size: 4 [unused]
|
|
// float4 xe_user_clip_planes[6]; // Offset: 16 Size: 96 [unused]
|
|
// float3 xe_ndc_scale; // Offset: 112 Size: 12 [unused]
|
|
// uint xe_pixel_pos_reg; // Offset: 124 Size: 4 [unused]
|
|
// float3 xe_ndc_offset; // Offset: 128 Size: 12 [unused]
|
|
// float xe_pixel_half_pixel_offset; // Offset: 140 Size: 4 [unused]
|
|
// float2 xe_point_size; // Offset: 144 Size: 8 [unused]
|
|
// float2 xe_point_size_min_max; // Offset: 152 Size: 8 [unused]
|
|
// float2 xe_point_screen_to_ndc; // Offset: 160 Size: 8 [unused]
|
|
// uint2 xe_sample_count_log2; // Offset: 168 Size: 8 [unused]
|
|
// float xe_alpha_test_reference; // Offset: 176 Size: 4 [unused]
|
|
// uint xe_edram_resolution_square_scale;// Offset: 180 Size: 4 [unused]
|
|
// uint xe_edram_pitch_tiles; // Offset: 184 Size: 4 [unused]
|
|
// uint xe_edram_depth_base_dwords; // Offset: 188 Size: 4 [unused]
|
|
// float4 xe_color_exp_bias; // Offset: 192 Size: 16 [unused]
|
|
// uint4 xe_color_output_map; // Offset: 208 Size: 16 [unused]
|
|
// float2 xe_tessellation_factor_range;// Offset: 224 Size: 8
|
|
// float2 xe_edram_depth_range; // Offset: 232 Size: 8 [unused]
|
|
// float2 xe_edram_poly_offset_front; // Offset: 240 Size: 8 [unused]
|
|
// float2 xe_edram_poly_offset_back; // Offset: 248 Size: 8 [unused]
|
|
// uint4 xe_edram_stencil[2]; // Offset: 256 Size: 32 [unused]
|
|
// uint4 xe_edram_rt_base_dwords_scaled;// Offset: 288 Size: 16 [unused]
|
|
// uint4 xe_edram_rt_format_flags; // Offset: 304 Size: 16 [unused]
|
|
// float4 xe_edram_rt_clamp[4]; // Offset: 320 Size: 64 [unused]
|
|
// uint4 xe_edram_rt_keep_mask[2]; // Offset: 384 Size: 32 [unused]
|
|
// uint4 xe_edram_rt_blend_factors_ops;// Offset: 416 Size: 16 [unused]
|
|
// float4 xe_edram_blend_constant; // Offset: 432 Size: 16 [unused]
|
|
//
|
|
// }
|
|
//
|
|
//
|
|
// Resource Bindings:
|
|
//
|
|
// Name Type Format Dim ID HLSL Bind Count
|
|
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
|
|
// xe_system_cbuffer cbuffer NA NA CB0 cb0 1
|
|
//
|
|
//
|
|
//
|
|
// Patch Constant signature:
|
|
//
|
|
// Name Index Mask Register SysValue Format Used
|
|
// -------------------- ----- ------ -------- -------- ------- ------
|
|
// SV_TessFactor 0 x 0 TRIEDGE float x
|
|
// SV_TessFactor 1 x 1 TRIEDGE float x
|
|
// SV_TessFactor 2 x 2 TRIEDGE float x
|
|
// SV_InsideTessFactor 0 x 3 TRIINT float x
|
|
//
|
|
//
|
|
// Input signature:
|
|
//
|
|
// Name Index Mask Register SysValue Format Used
|
|
// -------------------- ----- ------ -------- -------- ------- ------
|
|
// XEVERTEXID 0 x 0 NONE int x
|
|
//
|
|
//
|
|
// Output signature:
|
|
//
|
|
// Name Index Mask Register SysValue Format Used
|
|
// -------------------- ----- ------ -------- -------- ------- ------
|
|
// no Output
|
|
// Tessellation Domain # of control points
|
|
// -------------------- --------------------
|
|
// Triangle 3
|
|
//
|
|
// Tessellation Output Primitive Partitioning Type
|
|
// ------------------------------ ------------------
|
|
// Clockwise Triangles Even Fractional
|
|
//
|
|
hs_5_1
|
|
hs_decls
|
|
dcl_input_control_point_count 3
|
|
dcl_output_control_point_count 3
|
|
dcl_tessellator_domain domain_tri
|
|
dcl_tessellator_partitioning partitioning_fractional_even
|
|
dcl_tessellator_output_primitive output_triangle_cw
|
|
dcl_globalFlags refactoringAllowed
|
|
dcl_constantbuffer CB0[0:0][15], immediateIndexed, space=0
|
|
hs_control_point_phase
|
|
ret
|
|
hs_fork_phase
|
|
dcl_hs_fork_phase_instance_count 3
|
|
dcl_input vForkInstanceID
|
|
dcl_input vicp[3][0].x
|
|
dcl_output_siv o0.x, finalTriUeq0EdgeTessFactor
|
|
dcl_output_siv o1.x, finalTriVeq0EdgeTessFactor
|
|
dcl_output_siv o2.x, finalTriWeq0EdgeTessFactor
|
|
dcl_temps 1
|
|
dcl_indexrange o0.x 3
|
|
iadd r0.x, vForkInstanceID.x, l(1)
|
|
udiv null, r0.x, r0.x, l(3)
|
|
add r0.x, l(1.000000), vicp[r0.x + 0][0].x
|
|
max r0.x, r0.x, CB0[0][14].x
|
|
min r0.x, r0.x, CB0[0][14].y
|
|
mov r0.y, vForkInstanceID.x
|
|
mov o[r0.y + 0].x, r0.x
|
|
ret
|
|
hs_join_phase
|
|
dcl_input vpc0.x
|
|
dcl_input vpc1.x
|
|
dcl_input vpc2.x
|
|
dcl_output_siv o3.x, finalTriInsideTessFactor
|
|
dcl_temps 1
|
|
min r0.x, vpc0.x, vpc1.x
|
|
min o3.x, r0.x, vpc2.x
|
|
ret
|
|
// Approximately 12 instruction slots used
|