a769d70761
Implement SNaN detection and FPSCR exception tracking so that Rc=1 FPU instructions (fadds., fmadds., etc.) correctly update CR1 with FPSCR exception summary bits (FX, FEX, VX, OX). Previously these were hardcoded to zero. Enable ~2k tests that were previously disabled.
593 lines
16 KiB
C++
593 lines
16 KiB
C++
/*
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include "xenia/cpu/ppc/ppc_emit-private.h"
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#include "xenia/base/assert.h"
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#include "xenia/cpu/ppc/ppc_context.h"
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#include "xenia/cpu/ppc/ppc_hir_builder.h"
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#include <stddef.h>
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namespace xe {
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namespace cpu {
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namespace ppc {
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// TODO(benvanik): remove when enums redefined.
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using namespace xe::cpu::hir;
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using xe::cpu::hir::RoundMode;
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using xe::cpu::hir::Value;
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// Good source of information:
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// https://github.com/mamedev/historic-mame/blob/master/src/emu/cpu/powerpc/ppc_ops.c
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// The correctness of that code is not reflected here yet -_-
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// Enable rounding numbers to single precision as required.
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// This adds a bunch of work per operation and I'm not sure it's required.
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#define ROUND_TO_SINGLE
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// Floating-point arithmetic (A-8)
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int InstrEmit_faddx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- (frA) + (frB)
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Add(fra, frb);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frb);
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return 0;
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}
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int InstrEmit_faddsx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- (frA) + (frB)
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Add(fra, frb);
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v = f.ToSingle(v);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frb);
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return 0;
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}
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int InstrEmit_fdivx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- frA / frB
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Div(fra, frb);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frb);
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return 0;
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}
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int InstrEmit_fdivsx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- frA / frB
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Div(fra, frb);
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v = f.ToSingle(v);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frb);
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return 0;
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}
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int InstrEmit_fmulx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- (frA) x (frC)
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frc = f.LoadFPR(i.A.FRC);
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Value* v = f.Mul(fra, frc);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frc);
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return 0;
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}
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int InstrEmit_fmulsx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- (frA) x (frC)
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frc = f.LoadFPR(i.A.FRC);
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Value* v = f.Mul(fra, frc);
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v = f.ToSingle(v);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frc);
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return 0;
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}
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int InstrEmit_fresx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- 1.0 / (frB)
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// this actually does seem to require single precision, oddly
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// more research is needed
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Recip(f.Convert(frb, FLOAT32_TYPE));
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v = f.Convert(v, FLOAT64_TYPE); // f.ToSingle(v);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, frb);
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return 0;
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}
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int InstrEmit_frsqrtex(PPCHIRBuilder& f, const InstrData& i) {
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// Double precision:
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// frD <- 1/sqrt(frB)
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.RSqrt(frb);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, frb);
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return 0;
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}
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int InstrEmit_fsubx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- (frA) - (frB)
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Sub(fra, frb);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frb);
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return 0;
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}
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int InstrEmit_fsubsx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- (frA) - (frB)
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Sub(fra, frb);
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v = f.ToSingle(v);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frb);
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return 0;
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}
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int InstrEmit_fselx(PPCHIRBuilder& f, const InstrData& i) {
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// if (frA) >= 0.0
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// then frD <- (frC)
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// else frD <- (frB)
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Value* ge = f.CompareSGE(f.LoadFPR(i.A.FRA), f.LoadZeroFloat64());
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Value* v = f.Select(ge, f.LoadFPR(i.A.FRC), f.LoadFPR(i.A.FRB));
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc);
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return 0;
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}
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static int InstrEmit_fsqrt(PPCHIRBuilder& f, const InstrData& i, bool single) {
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// frD <- sqrt(frB)
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Sqrt(frb);
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if (single) {
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v = f.ToSingle(v);
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}
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, frb);
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return 0;
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}
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int InstrEmit_fsqrtx(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_fsqrt(f, i, false);
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}
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int InstrEmit_fsqrtsx(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_fsqrt(f, i, true);
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}
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// Floating-point multiply-add (A-9)
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static int InstrEmit_fmadd(PPCHIRBuilder& f, const InstrData& i, bool single) {
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// frD <- (frA x frC) + frB
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frc = f.LoadFPR(i.A.FRC);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.MulAdd(fra, frc, frb);
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if (single) {
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v = f.ToSingle(v);
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}
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frc, frb);
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return 0;
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}
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int InstrEmit_fmaddx(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_fmadd(f, i, false);
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}
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int InstrEmit_fmaddsx(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_fmadd(f, i, true);
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}
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static int InstrEmit_fmsub(PPCHIRBuilder& f, const InstrData& i, bool single) {
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// frD <- (frA x frC) - frB
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frc = f.LoadFPR(i.A.FRC);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.MulSub(fra, frc, frb);
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if (single) {
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v = f.ToSingle(v);
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}
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frc, frb);
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return 0;
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}
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int InstrEmit_fmsubx(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_fmsub(f, i, false);
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}
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int InstrEmit_fmsubsx(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_fmsub(f, i, true);
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}
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int InstrEmit_fnmaddx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- -([frA x frC] + frB)
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frc = f.LoadFPR(i.A.FRC);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Neg(f.MulAdd(fra, frc, frb));
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frc, frb);
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return 0;
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}
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int InstrEmit_fnmaddsx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- -([frA x frC] + frB)
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frc = f.LoadFPR(i.A.FRC);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Neg(f.MulAdd(fra, frc, frb));
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v = f.ToSingle(v);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frc, frb);
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return 0;
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}
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int InstrEmit_fnmsubx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- -([frA x frC] - frB)
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frc = f.LoadFPR(i.A.FRC);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Neg(f.MulSub(fra, frc, frb));
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frc, frb);
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return 0;
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}
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int InstrEmit_fnmsubsx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- -([frA x frC] - frB)
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Value* fra = f.LoadFPR(i.A.FRA);
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Value* frc = f.LoadFPR(i.A.FRC);
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Value* frb = f.LoadFPR(i.A.FRB);
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Value* v = f.Neg(f.MulSub(fra, frc, frb));
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v = f.ToSingle(v);
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f.StoreFPR(i.A.FRT, v);
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f.UpdateFPSCR(v, i.A.Rc, fra, frc, frb);
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return 0;
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}
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// Floating-point rounding and conversion (A-10)
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int InstrEmit_fcfidx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- signed_int64_to_double( frB )
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// Input is an integer bit pattern in FPR, not a float - no NaN detection.
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Value* v = f.Convert(f.Cast(f.LoadFPR(i.X.RB), INT64_TYPE), FLOAT64_TYPE);
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f.StoreFPR(i.X.RT, v);
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f.UpdateFPSCR(v, i.X.Rc);
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return 0;
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}
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int InstrEmit_fctidxx_(PPCHIRBuilder& f, const InstrData& i,
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RoundMode round_mode) {
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// Result is an integer bit pattern in FPR, not a float - no NaN detection.
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// NaN input is already handled explicitly by the branch.
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auto end = f.NewLabel();
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auto isnan = f.NewLabel();
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Value* v;
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Value* frb = f.LoadFPR(i.X.RB);
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f.BranchTrue(f.IsNan(frb), isnan);
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v = f.Convert(frb, INT64_TYPE, round_mode);
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v = f.Cast(v, FLOAT64_TYPE);
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f.StoreFPR(i.X.RT, v);
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f.UpdateFPSCR(v, i.X.Rc);
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f.Branch(end);
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f.MarkLabel(isnan);
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v = f.Cast(f.LoadConstantUint64(0x8000000000000000u), FLOAT64_TYPE);
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f.StoreFPR(i.X.RT, v);
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f.UpdateFPSCR(v, i.X.Rc);
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f.MarkLabel(end);
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return 0;
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}
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int InstrEmit_fctidx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- double_to_signed_int64( frB )
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return InstrEmit_fctidxx_(f, i, ROUND_DYNAMIC);
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}
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int InstrEmit_fctidzx(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_fctidxx_(f, i, ROUND_TO_ZERO);
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}
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int InstrEmit_fctiwxx_(PPCHIRBuilder& f, const InstrData& i,
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RoundMode round_mode) {
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// Result is an integer bit pattern in FPR, not a float - no NaN detection.
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// NaN input is already handled explicitly by the branch.
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auto end = f.NewLabel();
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auto isnan = f.NewLabel();
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Value* v;
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Value* frb = f.LoadFPR(i.X.RB);
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f.BranchTrue(f.IsNan(frb), isnan);
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v = f.Convert(frb, INT32_TYPE, round_mode);
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v = f.Cast(f.SignExtend(v, INT64_TYPE), FLOAT64_TYPE);
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f.StoreFPR(i.X.RT, v);
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f.UpdateFPSCR(v, i.X.Rc);
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f.Branch(end);
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f.MarkLabel(isnan);
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v = f.Cast(f.LoadConstantUint32(0x80000000u), FLOAT64_TYPE);
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f.StoreFPR(i.X.RT, v);
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f.UpdateFPSCR(v, i.X.Rc);
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f.MarkLabel(end);
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return 0;
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}
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int InstrEmit_fctiwx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- double_to_signed_int32( frB )
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return InstrEmit_fctiwxx_(f, i, ROUND_DYNAMIC);
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}
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int InstrEmit_fctiwzx(PPCHIRBuilder& f, const InstrData& i) {
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// TODO(benvanik): assuming round to zero is always set, is that ok?
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return InstrEmit_fctiwxx_(f, i, ROUND_TO_ZERO);
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}
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int InstrEmit_frspx(PPCHIRBuilder& f, const InstrData& i) {
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// frD <- Round_single(frB)
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Value* frb = f.LoadFPR(i.X.RB);
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Value* v = f.Convert(frb, FLOAT32_TYPE, ROUND_DYNAMIC);
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v = f.Convert(v, FLOAT64_TYPE);
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f.StoreFPR(i.X.RT, v);
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f.UpdateFPSCR(v, i.X.Rc, frb);
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return 0;
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}
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// Floating-point compare (A-11)
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int InstrEmit_fcmpx_(PPCHIRBuilder& f, const InstrData& i, bool ordered) {
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// if (FRA) is a NaN or (FRB) is a NaN then
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// c <- 0b0001
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// else if (FRA) < (FRB) then
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// c <- 0b1000
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// else if (FRA) > (FRB) then
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// c <- 0b0100
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// else {
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// c <- 0b0010
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// }
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// FPCC <- c
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// CR[4*BF:4*BF+3] <- c
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// if (FRA) is an SNaN or (FRB) is an SNaN then
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// VXSNAN <- 1
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// TODO(benvanik): update FPCC for mffsx/etc
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// TODO(benvanik): update VXSNAN
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const uint32_t crf = i.X.RT >> 2;
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Value* ra = f.LoadFPR(i.X.RA);
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Value* rb = f.LoadFPR(i.X.RB);
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Value* nan = f.Or(f.IsNan(ra), f.IsNan(rb));
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f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 3, nan);
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Value* not_nan = f.Xor(nan, f.LoadConstantInt8(0x01));
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Value* lt = f.And(not_nan, f.CompareSLT(ra, rb));
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f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 0, lt);
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Value* gt = f.And(not_nan, f.CompareSGT(ra, rb));
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f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 1, gt);
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Value* eq = f.And(not_nan, f.CompareEQ(ra, rb));
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f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 2, eq);
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return 0;
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}
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int InstrEmit_fcmpo(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_fcmpx_(f, i, true);
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}
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int InstrEmit_fcmpu(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_fcmpx_(f, i, false);
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}
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// Floating-point status and control register (A
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int InstrEmit_mcrfs(PPCHIRBuilder& f, const InstrData& i) {
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// mcrfs CRFD, CRFS
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// CR[4*CRFD:4*CRFD+3] <- FPSCR[4*CRFS:4*CRFS+3]
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// FPSCR[4*CRFS:4*CRFS+3] <- 0 (exception bits cleared)
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uint32_t crfd = i.X.RT >> 2; // Destination CR field
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uint32_t crfs = i.X.RA >> 2; // Source FPSCR field
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Value* fpscr = f.LoadFPSCR();
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// Extract 4-bit field from FPSCR
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// FPSCR fields are numbered from left to right (0-7), with field 0 being bits
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// 0-3
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uint32_t shift = 4 * (7 - crfs);
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Value* fpscr_field = f.And(f.Shr(fpscr, shift), f.LoadConstantUint32(0xF));
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// Store to CR field (need to shift to proper position in 64-bit CR)
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f.StoreCR(crfd, f.Shl(f.ZeroExtend(fpscr_field, INT64_TYPE), 4 * (7 - crfd)));
|
|
|
|
// Clear the FPSCR field (set to 0)
|
|
uint32_t mask = ~(0xF << shift);
|
|
f.StoreFPSCR(f.And(fpscr, f.LoadConstantUint32(mask)));
|
|
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_mffsx(PPCHIRBuilder& f, const InstrData& i) {
|
|
Value* v = f.Cast(f.ZeroExtend(f.LoadFPSCR(), INT64_TYPE), FLOAT64_TYPE);
|
|
f.StoreFPR(i.X.RT, v);
|
|
if (i.X.Rc) {
|
|
f.CopyFPSCRToCR1();
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_mtfsb0x(PPCHIRBuilder& f, const InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
int InstrEmit_mtfsb1x(PPCHIRBuilder& f, const InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
int InstrEmit_mtfsfx(PPCHIRBuilder& f, const InstrData& i) {
|
|
if (i.XFL.L) {
|
|
// Move/shift.
|
|
f.StoreFPSCR(
|
|
f.Truncate(f.Cast(f.LoadFPR(i.XFL.RB), INT64_TYPE), INT32_TYPE));
|
|
return 1;
|
|
} else {
|
|
assert_zero(i.XFL.W);
|
|
// Store under control of mask.
|
|
// Expand the mask from 8 bits -> 32 bits.
|
|
uint32_t mask = 0;
|
|
for (int j = 0; j < 8; j++) {
|
|
if (i.XFL.FM & (1 << (j ^ 7))) {
|
|
mask |= 0xF << (4 * j);
|
|
}
|
|
}
|
|
|
|
Value* v = f.Truncate(f.Cast(f.LoadFPR(i.XFL.RB), INT64_TYPE), INT32_TYPE);
|
|
if (mask != 0xFFFFFFFF) {
|
|
Value* fpscr = f.LoadFPSCR();
|
|
v = f.And(v, f.LoadConstantInt32(mask));
|
|
v = f.Or(v, f.And(fpscr, f.LoadConstantInt32(~mask)));
|
|
}
|
|
f.StoreFPSCR(v);
|
|
|
|
// Update the system rounding mode.
|
|
if (mask & 0x7) {
|
|
f.SetRoundingMode(f.And(v, f.LoadConstantInt32(7)));
|
|
}
|
|
}
|
|
if (i.XFL.Rc) {
|
|
f.CopyFPSCRToCR1();
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_mtfsfix(PPCHIRBuilder& f, const InstrData& i) {
|
|
// FPSCR[crfD] <- IMM
|
|
|
|
// Create a mask.
|
|
uint32_t mask = 0xF << (0x1C - (i.X.RT & 0x1C));
|
|
uint32_t value = i.X.RB << (0x1C - (i.X.RT & 0x1C));
|
|
|
|
Value* fpscr = f.LoadFPSCR();
|
|
fpscr = f.And(fpscr, f.LoadConstantInt32(~mask));
|
|
fpscr = f.Or(fpscr, f.LoadConstantInt32(value));
|
|
f.StoreFPSCR(fpscr);
|
|
|
|
// Update the system rounding mode.
|
|
if (mask & 0x7) {
|
|
f.SetRoundingMode(f.And(fpscr, f.LoadConstantInt32(7)));
|
|
}
|
|
|
|
if (i.X.Rc) {
|
|
f.CopyFPSCRToCR1();
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
// Floating-point move (A-21)
|
|
|
|
int InstrEmit_fabsx(PPCHIRBuilder& f, const InstrData& i) {
|
|
// frD <- abs(frB)
|
|
Value* v = f.Abs(f.LoadFPR(i.X.RB));
|
|
f.StoreFPR(i.X.RT, v);
|
|
/*
|
|
The contents of frB with bit 0 cleared are placed into frD.
|
|
Note that the fabs instruction treats NaNs just like any other kind of value.
|
|
That is, the sign bit of a NaN may be altered by fabs. This instruction does not
|
|
alter the FPSCR. Other registers altered: • Condition Register (CR1 field):
|
|
Affected: FX, FEX, VX, OX (if Rc = 1)
|
|
*/
|
|
// f.UpdateFPSCR(v, i.X.Rc);
|
|
if (i.X.Rc) {
|
|
// todo
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_fmrx(PPCHIRBuilder& f, const InstrData& i) {
|
|
// frD <- (frB)
|
|
Value* v = f.LoadFPR(i.X.RB);
|
|
f.StoreFPR(i.X.RT, v);
|
|
f.UpdateFPSCR(v, i.X.Rc);
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_fnabsx(PPCHIRBuilder& f, const InstrData& i) {
|
|
// frD <- !abs(frB)
|
|
Value* v = f.Neg(f.Abs(f.LoadFPR(i.X.RB)));
|
|
f.StoreFPR(i.X.RT, v);
|
|
// f.UpdateFPSCR(v, i.X.Rc);
|
|
if (i.X.Rc) {
|
|
// todo
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_fnegx(PPCHIRBuilder& f, const InstrData& i) {
|
|
// frD <- ¬ frB[0] || frB[1-63]
|
|
Value* v = f.Neg(f.LoadFPR(i.X.RB));
|
|
f.StoreFPR(i.X.RT, v);
|
|
// f.UpdateFPSCR(v, i.X.Rc);
|
|
if (i.X.Rc) {
|
|
// todo
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void RegisterEmitCategoryFPU() {
|
|
XEREGISTERINSTR(faddx);
|
|
XEREGISTERINSTR(faddsx);
|
|
XEREGISTERINSTR(fdivx);
|
|
XEREGISTERINSTR(fdivsx);
|
|
XEREGISTERINSTR(fmulx);
|
|
XEREGISTERINSTR(fmulsx);
|
|
XEREGISTERINSTR(fresx);
|
|
XEREGISTERINSTR(frsqrtex);
|
|
XEREGISTERINSTR(fsubx);
|
|
XEREGISTERINSTR(fsubsx);
|
|
XEREGISTERINSTR(fselx);
|
|
XEREGISTERINSTR(fsqrtx);
|
|
XEREGISTERINSTR(fsqrtsx);
|
|
XEREGISTERINSTR(fmaddx);
|
|
XEREGISTERINSTR(fmaddsx);
|
|
XEREGISTERINSTR(fmsubx);
|
|
XEREGISTERINSTR(fmsubsx);
|
|
XEREGISTERINSTR(fnmaddx);
|
|
XEREGISTERINSTR(fnmaddsx);
|
|
XEREGISTERINSTR(fnmsubx);
|
|
XEREGISTERINSTR(fnmsubsx);
|
|
XEREGISTERINSTR(fcfidx);
|
|
XEREGISTERINSTR(fctidx);
|
|
XEREGISTERINSTR(fctidzx);
|
|
XEREGISTERINSTR(fctiwx);
|
|
XEREGISTERINSTR(fctiwzx);
|
|
XEREGISTERINSTR(frspx);
|
|
XEREGISTERINSTR(fcmpo);
|
|
XEREGISTERINSTR(fcmpu);
|
|
XEREGISTERINSTR(mcrfs);
|
|
XEREGISTERINSTR(mffsx);
|
|
XEREGISTERINSTR(mtfsb0x);
|
|
XEREGISTERINSTR(mtfsb1x);
|
|
XEREGISTERINSTR(mtfsfx);
|
|
XEREGISTERINSTR(mtfsfix);
|
|
XEREGISTERINSTR(fabsx);
|
|
XEREGISTERINSTR(fmrx);
|
|
XEREGISTERINSTR(fnabsx);
|
|
XEREGISTERINSTR(fnegx);
|
|
}
|
|
|
|
} // namespace ppc
|
|
} // namespace cpu
|
|
} // namespace xe
|