35 lines
1.3 KiB
HLSL
35 lines
1.3 KiB
HLSL
#define XE_EDRAM_WRITE_ONLY
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#include "edram_load_store.hlsli"
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// Load4/Store4 aren't needed here, but 80x16 threads is over the limit.
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[numthreads(40, 16, 1)]
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void main(uint3 xe_group_id : SV_GroupID,
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uint3 xe_group_thread_id : SV_GroupThreadID,
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uint3 xe_thread_id : SV_DispatchThreadID) {
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uint4 clear_rect;
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clear_rect.xz = xe_edram_clear_rect & 0xFFFFu;
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clear_rect.yw = xe_edram_clear_rect >> 16u;
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uint2 sample_index = xe_thread_id.xy;
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sample_index.x *= 2u;
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[branch] if (any(sample_index < clear_rect.xy) ||
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any(sample_index >= clear_rect.zw)) {
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return;
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}
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uint2 tile_sample_index = xe_group_thread_id.xy;
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tile_sample_index.x *= 2u;
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bool second_sample_inside = sample_index.x + 1u < clear_rect.z;
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// 24-bit depth.
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uint edram_offset = XeEDRAMOffset32bpp(xe_group_id.xy, tile_sample_index);
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xe_edram_load_store_dest.Store(edram_offset, xe_edram_clear_depth24);
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[branch] if (second_sample_inside) {
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xe_edram_load_store_dest.Store(edram_offset + 4u, xe_edram_clear_depth24);
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}
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// 32-bit depth (pre-converted on the CPU).
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xe_edram_load_store_dest.Store(edram_offset + 10485760u,
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xe_edram_clear_depth32);
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[branch] if (second_sample_inside) {
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xe_edram_load_store_dest.Store(edram_offset + 10485764u,
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xe_edram_clear_depth32);
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}
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}
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