230 lines
7.0 KiB
C++
230 lines
7.0 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_FRONTEND_PPC_CONTEXT_H_
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#define XENIA_FRONTEND_PPC_CONTEXT_H_
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#include <cstdint>
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#include "xenia/base/vec128.h"
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namespace xe {
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namespace cpu {
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class Processor;
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class ThreadState;
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} // namespace cpu
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namespace kernel {
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class KernelState;
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} // namespace kernel
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} // namespace xe
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namespace xe {
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namespace cpu {
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namespace frontend {
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// Map:
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// 0-31: GPR
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// 32-63: FPR
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// 64: LR
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// 65: CTR
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// 66: XER
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// 67: FPSCR
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// 68: VSCR
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// 69-76: CR0-7
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// 100: invalid
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// 128-256: VR
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#pragma pack(push, 4)
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typedef struct alignas(64) PPCContext_s {
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// Must be stored at 0x0 for now.
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// TODO(benvanik): find a nice way to describe this to the JIT.
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ThreadState* thread_state;
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// TODO(benvanik): this is getting nasty. Must be here.
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uint8_t* virtual_membase;
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// Most frequently used registers first.
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uint64_t r[32]; // General purpose registers
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uint64_t lr; // Link register
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uint64_t ctr; // Count register
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// XER register
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// Split to make it easier to do individual updates.
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uint8_t xer_ca;
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uint8_t xer_ov;
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uint8_t xer_so;
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// Condition registers
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// These are split to make it easier to do DCE on unused stores.
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union {
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uint32_t value;
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struct {
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uint8_t cr0_lt; // Negative (LT) - result is negative
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uint8_t cr0_gt; // Positive (GT) - result is positive (and not zero)
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uint8_t cr0_eq; // Zero (EQ) - result is zero or a stwcx/stdcx completed
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// successfully
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uint8_t cr0_so; // Summary Overflow (SO) - copy of XER[SO]
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};
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} cr0;
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union {
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uint32_t value;
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struct {
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uint8_t cr1_fx; // FP exception summary - copy of FPSCR[FX]
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uint8_t cr1_fex; // FP enabled exception summary - copy of FPSCR[FEX]
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uint8_t
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cr1_vx; // FP invalid operation exception summary - copy of FPSCR[VX]
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uint8_t cr1_ox; // FP overflow exception - copy of FPSCR[OX]
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};
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} cr1;
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union {
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uint32_t value;
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struct {
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uint8_t cr2_0;
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uint8_t cr2_1;
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uint8_t cr2_2;
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uint8_t cr2_3;
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};
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} cr2;
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union {
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uint32_t value;
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struct {
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uint8_t cr3_0;
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uint8_t cr3_1;
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uint8_t cr3_2;
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uint8_t cr3_3;
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};
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} cr3;
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union {
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uint32_t value;
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struct {
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uint8_t cr4_0;
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uint8_t cr4_1;
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uint8_t cr4_2;
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uint8_t cr4_3;
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};
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} cr4;
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union {
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uint32_t value;
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struct {
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uint8_t cr5_0;
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uint8_t cr5_1;
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uint8_t cr5_2;
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uint8_t cr5_3;
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};
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} cr5;
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union {
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uint32_t value;
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struct {
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uint8_t cr6_all_equal;
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uint8_t cr6_1;
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uint8_t cr6_none_equal;
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uint8_t cr6_3;
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};
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} cr6;
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union {
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uint32_t value;
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struct {
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uint8_t cr7_0;
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uint8_t cr7_1;
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uint8_t cr7_2;
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uint8_t cr7_3;
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};
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} cr7;
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union {
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uint32_t value;
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struct {
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uint32_t rn : 2; // FP rounding control: 00 = nearest
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// 01 = toward zero
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// 10 = toward +infinity
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// 11 = toward -infinity
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uint32_t ni : 1; // Floating-point non-IEEE mode
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uint32_t xe : 1; // IEEE floating-point inexact exception enable
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uint32_t ze : 1; // IEEE floating-point zero divide exception enable
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uint32_t ue : 1; // IEEE floating-point underflow exception enable
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uint32_t oe : 1; // IEEE floating-point overflow exception enable
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uint32_t ve : 1; // FP invalid op exception enable
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uint32_t vxcvi : 1; // FP invalid op exception: invalid integer convert
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// -- sticky
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uint32_t vxsqrt : 1; // FP invalid op exception: invalid sqrt -- sticky
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uint32_t vxsoft : 1; // FP invalid op exception: software request
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// -- sticky
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uint32_t reserved : 1;
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uint32_t fprf_un : 1; // FP result unordered or NaN (FU or ?)
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uint32_t fprf_eq : 1; // FP result equal or zero (FE or =)
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uint32_t fprf_gt : 1; // FP result greater than or positive (FG or >)
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uint32_t fprf_lt : 1; // FP result less than or negative (FL or <)
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uint32_t fprf_c : 1; // FP result class
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uint32_t fi : 1; // FP fraction inexact
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uint32_t fr : 1; // FP fraction rounded
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uint32_t vxvc : 1; // FP invalid op exception: invalid compare --
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// sticky
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uint32_t vximz : 1; // FP invalid op exception: infinity * 0 -- sticky
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uint32_t vxzdz : 1; // FP invalid op exception: 0 / 0 -- sticky
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uint32_t vxidi : 1; // FP invalid op exception: infinity / infinity
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// -- sticky
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uint32_t vxisi : 1; // FP invalid op exception: infinity - infinity
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// -- sticky
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uint32_t vxsnan : 1; // FP invalid op exception: SNaN -- sticky
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uint32_t
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xx : 1; // FP inexact exception -- sticky
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uint32_t
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zx : 1; // FP zero divide exception -- sticky
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uint32_t
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ux : 1; // FP underflow exception -- sticky
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uint32_t
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ox : 1; // FP overflow exception -- sticky
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uint32_t vx : 1; // FP invalid operation exception summary
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uint32_t fex : 1; // FP enabled exception summary
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uint32_t
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fx : 1; // FP exception summary -- sticky
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} bits;
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} fpscr; // Floating-point status and control register
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uint8_t vscr_sat;
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double f[32]; // Floating-point registers
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vec128_t v[128]; // VMX128 vector registers
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// uint32_t get_fprf() {
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// return fpscr.value & 0x000F8000;
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// }
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// void set_fprf(const uint32_t v) {
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// fpscr.value = (fpscr.value & ~0x000F8000) | v;
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// }
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// Thread ID assigned to this context.
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uint32_t thread_id;
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// Reserve address for load acquire/store release. Shared.
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uint64_t* reserve_address;
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// Used to shuttle data into externs. Contents volatile.
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uint64_t scratch;
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// Processor-specific data pointer. Used on callbacks to get access to the
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// current runtime and its data.
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Processor* processor;
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// Shared kernel state, for easy access from kernel exports.
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xe::kernel::KernelState* kernel_state;
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uint8_t* physical_membase;
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void SetRegFromString(const char* name, const char* value);
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bool CompareRegWithString(const char* name, const char* value,
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char* out_value, size_t out_value_size);
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} PPCContext;
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#pragma pack(pop)
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} // namespace frontend
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} // namespace cpu
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} // namespace xe
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#endif // XENIA_FRONTEND_PPC_CONTEXT_H_
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