[iterate-4C] JIT Phase 1: native integer ALU emitters + differential tests
crates/xenia-jit/src/emit.rs: native x64 for the hot non-recording integer ALU ops — addi, addis, ori, oris, xori, xoris, or(x), and(x), xor(x), add(x), subf(x), neg(x). Each mirrors its interpreter arm exactly, then does pc+=4 and the cycle/timebase bumps. Per-instance guards fall back to the interpreter for forms the emitter can't yet reproduce faithfully: recording (`.`/Rc) forms, OE overflow forms, and the db16cyc spin hint (or r31,r31,r31 -> Yield). RA=0 literal-zero rule handled at emit time. Differential harness (tests.rs): each opcode run through interpret_one vs a JIT-compiled 1-instr block over 2000 random register seeds (+ edge values 0/0xFFFFFFFF/0x80000000/INT64 boundaries); asserts full GPR/PC/XER/cycle/ timebase/StepResult equality. Plus a guard test that recording/OE/db16cyc forms are NOT natively emitted. Gate: golden n200m BYTE-IDENTICAL with XENIA_JIT=1; `cargo test -p xenia-jit` green. Throughput -n 200M --gpu-inline: 4.3s interp, 6.2s JIT (down from 7.1s all-fallback skeleton). Still fallback-bound on loads/stores/branches -> Phase 2 is the crossover. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
MechaCat02
237
crates/xenia-jit/src/emit.rs
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237
crates/xenia-jit/src/emit.rs
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@@ -0,0 +1,237 @@
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//! Native x64 emitters for individual PPC opcodes (context-threading).
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//!
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//! Each emitter mirrors exactly one interpreter arm
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//! (`xenia-cpu/src/interpreter.rs`) and leaves guest state in `PpcContext`
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//! identical to what the interpreter would produce, then advances `pc` by 4 and
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//! bumps the cycle/timebase counters. Emitters cover only the cases they can
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//! reproduce faithfully; any variant they can't (recording `.` forms, `OE`
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//! overflow forms, the `db16cyc` spin hint) returns `false` from
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//! [`try_emit_native`] so the block falls back to the interpreter for that
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//! instruction — keeping every result byte-identical.
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//!
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//! Register convention (set up by the block prologue): `r15` = `*mut
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//! PpcContext`, `rbx` = `*mut JitEnv`. Emitters use `rax`/`rcx` as scratch
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//! (caller-saved; no cross-instruction state — all guest state lives in
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//! `PpcContext`). PPC operand roles follow the ISA: arithmetic D-forms write
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//! `rD` (`instr.rd()`); logical forms write `rA` (`instr.ra()`) from `rS`
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//! (`instr.rs()`).
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use dynasmrt::{DynasmApi, dynasm};
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use xenia_cpu::PpcOpcode;
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use xenia_cpu::context::PpcContext;
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use xenia_cpu::decoder::DecodedInstr;
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use crate::JitEnv;
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/// Byte offsets into `JitEnv`/`PpcContext`, resolved once per block compile.
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pub struct Offsets {
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pub env_ctx: i32,
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gpr: i32,
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pub pc: i32,
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pub cycle: i32,
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pub timebase: i32,
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}
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impl Offsets {
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pub fn resolve() -> Self {
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Offsets {
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env_ctx: core::mem::offset_of!(JitEnv, ctx) as i32,
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gpr: core::mem::offset_of!(PpcContext, gpr) as i32,
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pc: core::mem::offset_of!(PpcContext, pc) as i32,
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cycle: core::mem::offset_of!(PpcContext, cycle_count) as i32,
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timebase: core::mem::offset_of!(PpcContext, timebase) as i32,
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}
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}
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/// Byte offset of guest register `i` (`gpr[i]`, 8 bytes each).
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#[inline]
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fn gpr(&self, i: usize) -> i32 {
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self.gpr + (i as i32) * 8
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}
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}
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type Asm = dynasmrt::x64::Assembler;
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/// Emit `pc += 4; cycle_count += 1; timebase += 1` — the postlude every native
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/// (non-branch) opcode shares, matching `interpreter.rs` (`execute` does
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/// `ctx.pc += 4`, `step_block` bumps the counters after each instruction).
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#[inline]
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fn advance_and_count(ops: &mut Asm, off: &Offsets) {
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dynasm!(ops
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; .arch x64
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; add DWORD [r15 + off.pc], 4
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; inc QWORD [r15 + off.cycle]
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; inc QWORD [r15 + off.timebase]
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);
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}
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/// Try to emit native x64 for `instr`. Returns `true` if it fully handled the
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/// instruction (computation + `advance_and_count`); `false` if the caller must
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/// fall back to the interpreter for it.
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pub fn try_emit_native(ops: &mut Asm, off: &Offsets, instr: &DecodedInstr) -> bool {
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let ra = instr.ra();
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let rb = instr.rb();
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let rd = instr.rd(); // == rs()
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match instr.opcode {
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// rD = (rA==0 ? 0 : gpr[rA]) + EXTS(SIMM) [64-bit; never records]
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PpcOpcode::addi => {
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let simm = instr.simm16() as i32; // fits i32 (16-bit sign-extended)
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load_ra_or_zero(ops, off, ra);
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if simm != 0 {
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dynasm!(ops ; .arch x64 ; add rax, simm);
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}
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dynasm!(ops ; .arch x64 ; mov [r15 + off.gpr(rd)], rax);
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advance_and_count(ops, off);
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true
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}
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// rD = (rA==0 ? 0 : gpr[rA]) + (EXTS(SIMM) << 16) [64-bit]
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PpcOpcode::addis => {
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// (i16 sign-extended) << 16 occupies bits 16..31 with the sign in
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// bit 31 — exactly an i32, so it fits an `add r64, imm32`.
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let simm = (instr.simm16() as i32) << 16;
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load_ra_or_zero(ops, off, ra);
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if simm != 0 {
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dynasm!(ops ; .arch x64 ; add rax, simm);
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}
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dynasm!(ops ; .arch x64 ; mov [r15 + off.gpr(rd)], rax);
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advance_and_count(ops, off);
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true
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}
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// gpr[rA] = gpr[rS] | ZEXT(UIMM) [never records]
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PpcOpcode::ori => {
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let uimm = instr.uimm16() as i32; // 0..65535 -> positive i32 (zext == sext)
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dynasm!(ops ; .arch x64 ; mov rax, [r15 + off.gpr(rd)]);
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if uimm != 0 {
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dynasm!(ops ; .arch x64 ; or rax, uimm);
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}
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dynasm!(ops ; .arch x64 ; mov [r15 + off.gpr(ra)], rax);
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advance_and_count(ops, off);
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true
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}
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// gpr[rA] = gpr[rS] | (ZEXT(UIMM) << 16)
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PpcOpcode::oris => {
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let imm = (instr.uimm16() as u32) << 16;
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(rd)]
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; mov ecx, imm as i32 // zero-extends into rcx
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; or rax, rcx
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; mov [r15 + off.gpr(ra)], rax
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);
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advance_and_count(ops, off);
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true
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}
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// gpr[rA] = gpr[rS] ^ ZEXT(UIMM)
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PpcOpcode::xori => {
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let uimm = instr.uimm16() as i32;
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dynasm!(ops ; .arch x64 ; mov rax, [r15 + off.gpr(rd)]);
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if uimm != 0 {
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dynasm!(ops ; .arch x64 ; xor rax, uimm);
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}
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dynasm!(ops ; .arch x64 ; mov [r15 + off.gpr(ra)], rax);
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advance_and_count(ops, off);
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true
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}
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// gpr[rA] = gpr[rS] ^ (ZEXT(UIMM) << 16)
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PpcOpcode::xoris => {
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let imm = (instr.uimm16() as u32) << 16;
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(rd)]
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; mov ecx, imm as i32
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; xor rax, rcx
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; mov [r15 + off.gpr(ra)], rax
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);
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advance_and_count(ops, off);
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true
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}
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// gpr[rA] = gpr[rS] | gpr[rB] [64-bit]. Skip the db16cyc spin hint
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// (returns Yield) and the recording form.
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PpcOpcode::orx => {
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if instr.rc_bit() || instr.raw == 0x7FFF_FB78 {
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return false;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(rd)]
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; or rax, [r15 + off.gpr(rb)]
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; mov [r15 + off.gpr(ra)], rax
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);
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advance_and_count(ops, off);
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true
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}
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// gpr[rA] = gpr[rS] & gpr[rB] [64-bit]
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PpcOpcode::andx => {
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if instr.rc_bit() {
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return false;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(rd)]
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; and rax, [r15 + off.gpr(rb)]
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; mov [r15 + off.gpr(ra)], rax
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);
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advance_and_count(ops, off);
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true
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}
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// gpr[rA] = gpr[rS] ^ gpr[rB] [64-bit]
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PpcOpcode::xorx => {
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if instr.rc_bit() {
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return false;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(rd)]
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; xor rax, [r15 + off.gpr(rb)]
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; mov [r15 + off.gpr(ra)], rax
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);
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advance_and_count(ops, off);
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true
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}
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// rD = gpr[rA] + gpr[rB] [64-bit]; skip OE/recording forms.
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PpcOpcode::addx => {
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if instr.oe() || instr.rc_bit() {
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return false;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(ra)]
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; add rax, [r15 + off.gpr(rb)]
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; mov [r15 + off.gpr(rd)], rax
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);
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advance_and_count(ops, off);
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true
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}
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// rD = gpr[rB] - gpr[rA] [64-bit]; skip OE/recording forms.
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PpcOpcode::subfx => {
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if instr.oe() || instr.rc_bit() {
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return false;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(rb)]
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; sub rax, [r15 + off.gpr(ra)]
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; mov [r15 + off.gpr(rd)], rax
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);
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advance_and_count(ops, off);
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true
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}
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// rD = 0 - gpr[rA] [64-bit]; skip OE/recording forms.
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PpcOpcode::negx => {
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if instr.oe() || instr.rc_bit() {
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return false;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(ra)]
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; neg rax
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; mov [r15 + off.gpr(rd)], rax
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);
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advance_and_count(ops, off);
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true
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}
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_ => false,
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}
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}
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/// Load `gpr[ra]` into `rax`, or zero `rax` when `ra == 0` (the PPC
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/// arithmetic-D "RA=0 means literal 0" rule, statically known here).
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#[inline]
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fn load_ra_or_zero(ops: &mut Asm, off: &Offsets, ra: usize) {
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if ra == 0 {
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dynasm!(ops ; .arch x64 ; xor eax, eax);
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} else {
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dynasm!(ops ; .arch x64 ; mov rax, [r15 + off.gpr(ra)]);
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}
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}
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@@ -37,6 +37,10 @@ use xenia_cpu::decoder::DecodedInstr;
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use xenia_cpu::interpreter::{StepResult, interpret_one};
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use xenia_memory::MemoryAccess;
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mod emit;
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#[cfg(test)]
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mod tests;
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/// Runtime environment handed to a compiled block. The emitted prologue reads
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/// only `ctx` (via `offset_of!`); `mem` and `last_result` are touched solely by
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/// the Rust helpers. `mem` is a real fat raw pointer, so no transmute is needed
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@@ -124,10 +128,7 @@ fn compile_block(block: &DecodedBlock) -> CompiledBlock {
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let instrs: Box<[DecodedInstr]> = block.instrs.clone().into_boxed_slice();
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// Field offsets resolved at compile time — robust to struct layout.
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let off_ctx = core::mem::offset_of!(JitEnv, ctx) as i32;
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let off_cycle = core::mem::offset_of!(PpcContext, cycle_count) as i32;
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let off_timebase = core::mem::offset_of!(PpcContext, timebase) as i32;
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let off_pc = core::mem::offset_of!(PpcContext, pc) as i32;
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let off = emit::Offsets::resolve();
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let helper = jit_interpret_one as usize as i64;
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let mut ops = dynasmrt::x64::Assembler::new().expect("dynasm assembler");
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@@ -144,10 +145,17 @@ fn compile_block(block: &DecodedBlock) -> CompiledBlock {
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; push r15
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; sub rsp, 8
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; mov rbx, rdi
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; mov r15, [rbx + off_ctx]
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; mov r15, [rbx + off.env_ctx]
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);
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for instr in instrs.iter() {
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// Native fast path: emitters fully handle the instruction (compute +
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// pc+=4 + counter bumps) and never diverge control flow, so no exit
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// checks are needed after them.
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if emit::try_emit_native(&mut ops, &off, instr) {
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continue;
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}
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// Interpreter fallback for un-ported opcodes.
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let instr_ptr = instr as *const DecodedInstr as usize as i64;
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let expected_next = instr.addr.wrapping_add(4) as i32;
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dynasm!(ops
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@@ -158,13 +166,13 @@ fn compile_block(block: &DecodedBlock) -> CompiledBlock {
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; mov rax, QWORD helper
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; call rax
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// determinism postlude: cycle_count += 1; timebase += 1
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; inc QWORD [r15 + off_cycle]
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; inc QWORD [r15 + off_timebase]
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; inc QWORD [r15 + off.cycle]
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; inc QWORD [r15 + off.timebase]
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// non-Continue result -> exit returning the discriminant in eax
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; test eax, eax
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; jnz =>l_exit
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// taken-branch (pc discontinuity) -> stop the block, return Continue
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; cmp DWORD [r15 + off_pc], expected_next
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; cmp DWORD [r15 + off.pc], expected_next
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; jne =>l_cont
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);
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}
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223
crates/xenia-jit/src/tests.rs
Normal file
223
crates/xenia-jit/src/tests.rs
Normal file
@@ -0,0 +1,223 @@
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//! Differential opcode tests: for each natively-emitted opcode, run a random
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//! register state through the interpreter (`interpret_one`, then the same
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//! per-instruction counter bump `step_block` does) and through a JIT-compiled
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//! one-instruction block, and assert the resulting `PpcContext` (GPRs, PC,
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//! XER, CR, cycle/timebase) and `StepResult` are identical. This makes the
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//! hand-written x64 as trustworthy as the interpreter.
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use super::{CompiledBlock, compile_block, run_jit_block};
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use crate::emit;
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use xenia_cpu::block_cache::DecodedBlock;
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use xenia_cpu::context::PpcContext;
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use xenia_cpu::decode;
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use xenia_cpu::decoder::DecodedInstr;
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use xenia_cpu::interpreter::interpret_one;
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use xenia_memory::MemoryAccess;
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/// Memory that must never be touched — the ALU opcodes tested here don't
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/// access guest memory, so any call is a bug in the emitter.
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struct NoMem;
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impl MemoryAccess for NoMem {
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fn read_u8(&self, _: u32) -> u8 {
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unreachable!("ALU emitter touched memory (read_u8)")
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}
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fn read_u16(&self, _: u32) -> u16 {
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unreachable!("ALU emitter touched memory (read_u16)")
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}
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fn read_u32(&self, _: u32) -> u32 {
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unreachable!("ALU emitter touched memory (read_u32)")
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}
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fn read_u64(&self, _: u32) -> u64 {
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unreachable!("ALU emitter touched memory (read_u64)")
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}
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fn write_u8(&self, _: u32, _: u8) {
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unreachable!("ALU emitter touched memory (write_u8)")
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}
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fn write_u16(&self, _: u32, _: u16) {
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unreachable!("ALU emitter touched memory (write_u16)")
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}
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fn write_u32(&self, _: u32, _: u32) {
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unreachable!("ALU emitter touched memory (write_u32)")
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}
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fn write_u64(&self, _: u32, _: u64) {
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unreachable!("ALU emitter touched memory (write_u64)")
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}
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fn translate(&self, _: u32) -> Option<*const u8> {
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None
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}
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fn translate_mut(&self, _: u32) -> Option<*mut u8> {
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None
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}
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}
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// ---- instruction encoders (PPC big-endian field layout; `raw` is the u32) ----
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/// D-form: `op | b6_10<<21 | b11_15<<16 | imm16`.
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fn enc_d(op: u32, b6_10: u32, b11_15: u32, imm16: u16) -> u32 {
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(op << 26) | (b6_10 << 21) | (b11_15 << 16) | (imm16 as u32)
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}
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/// X-form (logical register): `op | b6_10<<21 | b11_15<<16 | b16_20<<11 | xo<<1 | rc`.
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fn enc_x(op: u32, b6_10: u32, b11_15: u32, b16_20: u32, xo: u32, rc: u32) -> u32 {
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(op << 26) | (b6_10 << 21) | (b11_15 << 16) | (b16_20 << 11) | (xo << 1) | rc
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}
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/// XO-form (arithmetic register): X-form plus the OE bit at position 10.
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fn enc_xo(op: u32, b6_10: u32, b11_15: u32, b16_20: u32, oe: u32, xo: u32, rc: u32) -> u32 {
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(op << 26) | (b6_10 << 21) | (b11_15 << 16) | (b16_20 << 11) | (oe << 10) | (xo << 1) | rc
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}
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/// Deterministic PRNG (splitmix64-ish) so failures are reproducible.
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fn rng(state: &mut u64) -> u64 {
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*state = state.wrapping_add(0x9E37_79B9_7F4A_7C15);
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let mut z = *state;
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z = (z ^ (z >> 30)).wrapping_mul(0xBF58_476D_1CE4_E5B9);
|
||||
z = (z ^ (z >> 27)).wrapping_mul(0x94D0_49BB_1331_11EB);
|
||||
z ^ (z >> 31)
|
||||
}
|
||||
|
||||
fn ctx_from_gpr(gpr: [u64; 32], pc: u32) -> PpcContext {
|
||||
let mut c = PpcContext::new();
|
||||
c.gpr = gpr;
|
||||
c.pc = pc;
|
||||
c
|
||||
}
|
||||
|
||||
/// Assert the JIT emits `raw` natively and reproduces the interpreter exactly
|
||||
/// for the given register seed.
|
||||
fn check(raw: u32, gpr: [u64; 32]) {
|
||||
let pc = 0x8200_1000u32;
|
||||
let instr: DecodedInstr = decode(raw, pc);
|
||||
let off = emit::Offsets::resolve();
|
||||
|
||||
// Guard: the opcode must actually be natively emitted (else this test is
|
||||
// vacuous — a fallback would trivially match).
|
||||
let mut probe = dynasmrt::x64::Assembler::new().unwrap();
|
||||
assert!(
|
||||
emit::try_emit_native(&mut probe, &off, &instr),
|
||||
"opcode not natively emitted for raw={raw:#010x} ({:?})",
|
||||
instr.opcode
|
||||
);
|
||||
|
||||
// Interpreter reference: interpret_one, then the counter bump step_block does.
|
||||
let mem = NoMem;
|
||||
let mut a = ctx_from_gpr(gpr, pc);
|
||||
let ra = interpret_one(&mut a, &mem, &instr);
|
||||
a.cycle_count += 1;
|
||||
a.timebase += 1;
|
||||
|
||||
// JIT.
|
||||
let mut b = ctx_from_gpr(gpr, pc);
|
||||
let block = DecodedBlock {
|
||||
start_pc: pc,
|
||||
end_pc: pc.wrapping_add(4),
|
||||
page_version: 0,
|
||||
instrs: vec![instr],
|
||||
sync_sensitive: false,
|
||||
};
|
||||
let cb: CompiledBlock = compile_block(&block);
|
||||
let rb = run_jit_block(&cb, &mut b, &mem);
|
||||
|
||||
assert_eq!(a.gpr, b.gpr, "gpr mismatch raw={raw:#010x} ({:?})", instr.opcode);
|
||||
assert_eq!(a.pc, b.pc, "pc mismatch raw={raw:#010x}");
|
||||
assert_eq!(a.cycle_count, b.cycle_count, "cycle mismatch raw={raw:#010x}");
|
||||
assert_eq!(a.timebase, b.timebase, "timebase mismatch raw={raw:#010x}");
|
||||
assert_eq!(a.xer_ca, b.xer_ca, "xer_ca mismatch raw={raw:#010x}");
|
||||
assert_eq!(a.xer_ov, b.xer_ov, "xer_ov mismatch raw={raw:#010x}");
|
||||
assert_eq!(a.xer_so, b.xer_so, "xer_so mismatch raw={raw:#010x}");
|
||||
assert_eq!(ra, rb, "StepResult mismatch raw={raw:#010x}");
|
||||
}
|
||||
|
||||
/// Random register seeds, including hard boundary values in a few slots.
|
||||
fn fuzz_gpr(seed: &mut u64) -> [u64; 32] {
|
||||
let mut g = [0u64; 32];
|
||||
for slot in g.iter_mut() {
|
||||
*slot = rng(seed);
|
||||
}
|
||||
// Sprinkle in edge values.
|
||||
g[0] = 0;
|
||||
g[3] = 0xFFFF_FFFF;
|
||||
g[4] = 0x8000_0000;
|
||||
g[5] = 0xFFFF_FFFF_FFFF_FFFF;
|
||||
g[6] = 0x0000_0000_8000_0000;
|
||||
g
|
||||
}
|
||||
|
||||
const ITERS: usize = 2000;
|
||||
|
||||
#[test]
|
||||
fn addi_matches() {
|
||||
let mut s = 0x1234u64;
|
||||
for _ in 0..ITERS {
|
||||
let g = fuzz_gpr(&mut s);
|
||||
let rd = (rng(&mut s) % 32) as u32;
|
||||
let ra = (rng(&mut s) % 32) as u32;
|
||||
let imm = rng(&mut s) as u16;
|
||||
check(enc_d(14, rd, ra, imm), g); // addi
|
||||
check(enc_d(15, rd, ra, imm), g); // addis
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn logical_imm_matches() {
|
||||
let mut s = 0x5678u64;
|
||||
for _ in 0..ITERS {
|
||||
let g = fuzz_gpr(&mut s);
|
||||
let rs = (rng(&mut s) % 32) as u32;
|
||||
let ra = (rng(&mut s) % 32) as u32;
|
||||
let uimm = rng(&mut s) as u16;
|
||||
check(enc_d(24, rs, ra, uimm), g); // ori
|
||||
check(enc_d(25, rs, ra, uimm), g); // oris
|
||||
check(enc_d(26, rs, ra, uimm), g); // xori
|
||||
check(enc_d(27, rs, ra, uimm), g); // xoris
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn logical_reg_matches() {
|
||||
let mut s = 0x9abcu64;
|
||||
for _ in 0..ITERS {
|
||||
let g = fuzz_gpr(&mut s);
|
||||
let rs = (rng(&mut s) % 32) as u32;
|
||||
let ra = (rng(&mut s) % 32) as u32;
|
||||
let rb = (rng(&mut s) % 32) as u32;
|
||||
check(enc_x(31, rs, ra, rb, 444, 0), g); // or
|
||||
check(enc_x(31, rs, ra, rb, 28, 0), g); // and
|
||||
check(enc_x(31, rs, ra, rb, 316, 0), g); // xor
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn arith_reg_matches() {
|
||||
let mut s = 0xdef0u64;
|
||||
for _ in 0..ITERS {
|
||||
let g = fuzz_gpr(&mut s);
|
||||
let rd = (rng(&mut s) % 32) as u32;
|
||||
let ra = (rng(&mut s) % 32) as u32;
|
||||
let rb = (rng(&mut s) % 32) as u32;
|
||||
check(enc_xo(31, rd, ra, rb, 0, 266, 0), g); // add
|
||||
check(enc_xo(31, rd, ra, rb, 0, 40, 0), g); // subf
|
||||
check(enc_xo(31, rd, ra, rb, 0, 104, 0), g); // neg (rb ignored)
|
||||
}
|
||||
}
|
||||
|
||||
/// The recording/OE forms and the db16cyc hint must NOT be natively emitted
|
||||
/// (they fall back to the interpreter). Guards against a future emitter
|
||||
/// accidentally handling a form it can't reproduce.
|
||||
#[test]
|
||||
fn recording_and_hint_forms_fall_back() {
|
||||
let off = emit::Offsets::resolve();
|
||||
let mut probe = dynasmrt::x64::Assembler::new().unwrap();
|
||||
let cases = [
|
||||
enc_xo(31, 3, 4, 5, 0, 266, 1), // add.
|
||||
enc_xo(31, 3, 4, 5, 1, 266, 0), // addo
|
||||
enc_x(31, 3, 4, 5, 444, 1), // or.
|
||||
0x7FFF_FB78u32, // db16cyc (or r31,r31,r31)
|
||||
];
|
||||
for raw in cases {
|
||||
let instr = decode(raw, 0x8200_1000);
|
||||
assert!(
|
||||
!emit::try_emit_native(&mut probe, &off, &instr),
|
||||
"raw={raw:#010x} ({:?}) should fall back, not native",
|
||||
instr.opcode
|
||||
);
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user