[iterate-4C] JIT Phase 2b-ii: native branches (bx/bcx/bclrx)
try_emit_native now returns a 3-state Emit enum (Fallback/Native/Branch); compile_block appends the pc==expected_next discontinuity check after a native branch, mirroring step_block. bx (aa/rel, lk), bcx (CTR decrement + CTR/CR condition, cmov-selected target), bclrx (return via lr & !3) emitted natively; bcctrx stays on fallback (dispatch_rec side effect). count_only postlude (counters, no pc+=4) for branches. Differential tests: unconditional/conditional/return branches over exhaustive BO bits, CTR==1->0 boundary, lr alignment mask, both lk states, asserting pc/lr/ctr/cr/counters. Golden n200m BYTE-IDENTICAL with and without XENIA_JIT (11 tests green). Throughput 4.85->4.7s (interp ~3.9s); crossover still pending rotate/shift (Phase 3). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
MechaCat02
@@ -23,6 +23,20 @@ use xenia_cpu::decoder::DecodedInstr;
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use crate::JitEnv;
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/// Outcome of trying to emit one instruction natively.
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum Emit {
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/// Not handled — the caller must emit the interpreter fallback + exit checks.
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Fallback,
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/// Fully handled; `pc += 4` and control always continues to the next
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/// instruction (no exit check needed).
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Native,
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/// Handled, but the instruction may change `pc` discontinuously (a branch).
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/// The caller must append the `pc == expected_next` check so a taken branch
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/// ends the block and a fall-through continues — exactly like `step_block`.
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Branch,
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}
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/// Which byte within a `CrField` — used to address the individual condition
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/// flags the emitters write with `setcc`.
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#[derive(Clone, Copy)]
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@@ -40,6 +54,10 @@ pub struct Offsets {
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pub pc: i32,
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pub cycle: i32,
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pub timebase: i32,
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/// Link register (`lr: u64`).
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lr: i32,
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/// Count register (`ctr: u64`).
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ctr: i32,
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/// Base of the `cr: [CrField; 8]` array.
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cr: i32,
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/// Stride between adjacent `CrField`s (`size_of::<CrField>()`).
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@@ -62,6 +80,8 @@ impl Offsets {
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pc: core::mem::offset_of!(PpcContext, pc) as i32,
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cycle: core::mem::offset_of!(PpcContext, cycle_count) as i32,
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timebase: core::mem::offset_of!(PpcContext, timebase) as i32,
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lr: core::mem::offset_of!(PpcContext, lr) as i32,
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ctr: core::mem::offset_of!(PpcContext, ctr) as i32,
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cr: core::mem::offset_of!(PpcContext, cr) as i32,
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cr_stride: core::mem::size_of::<CrField>() as i32,
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cr_lt: core::mem::offset_of!(CrField, lt) as i32,
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@@ -87,6 +107,20 @@ impl Offsets {
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};
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self.cr + (field as i32) * self.cr_stride + within
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}
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/// Byte offset of absolute CR bit `bit` (0-31), matching
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/// `PpcContext::get_cr_bit`: `field = bit/4`, `sub = bit%4` →
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/// `lt/gt/eq/so`. The byte holds the flag as 0/1.
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#[inline]
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fn cr_bit_off(&self, bit: u32) -> i32 {
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let field = (bit / 4) as usize;
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let which = match bit % 4 {
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0 => CrByte::Lt,
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1 => CrByte::Gt,
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2 => CrByte::Eq,
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_ => CrByte::So,
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};
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self.cr_byte(field, which)
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}
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}
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type Asm = dynasmrt::x64::Assembler;
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@@ -104,15 +138,27 @@ fn advance_and_count(ops: &mut Asm, off: &Offsets) {
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);
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}
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/// Try to emit native x64 for `instr`. Returns `true` if it fully handled the
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/// instruction (computation + `advance_and_count`); `false` if the caller must
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/// fall back to the interpreter for it.
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/// Emit `cycle_count += 1; timebase += 1` WITHOUT touching `pc` — the postlude
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/// for native branches, which set `pc` themselves.
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#[inline]
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fn count_only(ops: &mut Asm, off: &Offsets) {
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dynasm!(ops
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; .arch x64
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; inc QWORD [r15 + off.cycle]
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; inc QWORD [r15 + off.timebase]
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);
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}
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/// Try to emit native x64 for `instr`. Returns [`Emit::Native`] if it fully
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/// handled the instruction (computation + `advance_and_count`), [`Emit::Branch`]
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/// if it handled a branch (caller must add the pc-discontinuity exit check), or
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/// [`Emit::Fallback`] if the caller must fall back to the interpreter.
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pub fn try_emit_native(
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ops: &mut Asm,
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off: &Offsets,
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helpers: &crate::MemHelpers,
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instr: &DecodedInstr,
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) -> bool {
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) -> Emit {
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let ra = instr.ra();
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let rb = instr.rb();
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let rd = instr.rd(); // == rs()
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@@ -126,7 +172,7 @@ pub fn try_emit_native(
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}
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dynasm!(ops ; .arch x64 ; mov [r15 + off.gpr(rd)], rax);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// rD = (rA==0 ? 0 : gpr[rA]) + (EXTS(SIMM) << 16) [64-bit]
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PpcOpcode::addis => {
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@@ -139,7 +185,7 @@ pub fn try_emit_native(
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}
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dynasm!(ops ; .arch x64 ; mov [r15 + off.gpr(rd)], rax);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// gpr[rA] = gpr[rS] | ZEXT(UIMM) [never records]
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PpcOpcode::ori => {
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@@ -150,7 +196,7 @@ pub fn try_emit_native(
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}
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dynasm!(ops ; .arch x64 ; mov [r15 + off.gpr(ra)], rax);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// gpr[rA] = gpr[rS] | (ZEXT(UIMM) << 16)
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PpcOpcode::oris => {
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@@ -162,7 +208,7 @@ pub fn try_emit_native(
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; mov [r15 + off.gpr(ra)], rax
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);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// gpr[rA] = gpr[rS] ^ ZEXT(UIMM)
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PpcOpcode::xori => {
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@@ -173,7 +219,7 @@ pub fn try_emit_native(
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}
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dynasm!(ops ; .arch x64 ; mov [r15 + off.gpr(ra)], rax);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// gpr[rA] = gpr[rS] ^ (ZEXT(UIMM) << 16)
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PpcOpcode::xoris => {
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@@ -185,13 +231,13 @@ pub fn try_emit_native(
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; mov [r15 + off.gpr(ra)], rax
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);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// gpr[rA] = gpr[rS] | gpr[rB] [64-bit]. Skip the db16cyc spin hint
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// (returns Yield) and the recording form.
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PpcOpcode::orx => {
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if instr.rc_bit() || instr.raw == 0x7FFF_FB78 {
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return false;
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return Emit::Fallback;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(rd)]
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@@ -199,12 +245,12 @@ pub fn try_emit_native(
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; mov [r15 + off.gpr(ra)], rax
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);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// gpr[rA] = gpr[rS] & gpr[rB] [64-bit]
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PpcOpcode::andx => {
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if instr.rc_bit() {
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return false;
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return Emit::Fallback;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(rd)]
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@@ -212,12 +258,12 @@ pub fn try_emit_native(
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; mov [r15 + off.gpr(ra)], rax
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);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// gpr[rA] = gpr[rS] ^ gpr[rB] [64-bit]
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PpcOpcode::xorx => {
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if instr.rc_bit() {
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return false;
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return Emit::Fallback;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(rd)]
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@@ -225,12 +271,12 @@ pub fn try_emit_native(
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; mov [r15 + off.gpr(ra)], rax
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);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// rD = gpr[rA] + gpr[rB] [64-bit]; skip OE/recording forms.
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PpcOpcode::addx => {
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if instr.oe() || instr.rc_bit() {
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return false;
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return Emit::Fallback;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(ra)]
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@@ -238,12 +284,12 @@ pub fn try_emit_native(
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; mov [r15 + off.gpr(rd)], rax
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);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// rD = gpr[rB] - gpr[rA] [64-bit]; skip OE/recording forms.
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PpcOpcode::subfx => {
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if instr.oe() || instr.rc_bit() {
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return false;
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return Emit::Fallback;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(rb)]
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@@ -251,12 +297,12 @@ pub fn try_emit_native(
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; mov [r15 + off.gpr(rd)], rax
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);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// rD = 0 - gpr[rA] [64-bit]; skip OE/recording forms.
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PpcOpcode::negx => {
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if instr.oe() || instr.rc_bit() {
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return false;
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return Emit::Fallback;
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}
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dynasm!(ops ; .arch x64
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; mov rax, [r15 + off.gpr(ra)]
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@@ -264,7 +310,7 @@ pub fn try_emit_native(
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; mov [r15 + off.gpr(rd)], rax
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);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// ===== Compares: cr[bf] = { lt, gt, eq, so=xer_so!=0 } =====
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// cr[bf] = signed(ra ? imm) [L: 64-bit, else 32-bit]
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@@ -278,7 +324,7 @@ pub fn try_emit_native(
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}
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emit_cr_from_flags(ops, off, bf, /*signed=*/ true);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// cr[bf] = unsigned(ra ? imm)
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PpcOpcode::cmpli => {
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@@ -291,7 +337,7 @@ pub fn try_emit_native(
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}
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emit_cr_from_flags(ops, off, bf, /*signed=*/ false);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// cr[bf] = signed(ra ? rb)
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PpcOpcode::cmp => {
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@@ -311,7 +357,7 @@ pub fn try_emit_native(
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}
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emit_cr_from_flags(ops, off, bf, /*signed=*/ true);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// cr[bf] = unsigned(ra ? rb)
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PpcOpcode::cmpl => {
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@@ -331,50 +377,162 @@ pub fn try_emit_native(
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}
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emit_cr_from_flags(ops, off, bf, /*signed=*/ false);
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advance_and_count(ops, off);
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true
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Emit::Native
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}
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// ===== Loads (D-form): rD = EXT(mem[(rA==0?0:gpr[rA]) + EXTS(D)]) =====
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PpcOpcode::lbz => {
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emit_load(ops, off, helpers.read_u8, ra, rd, instr.d(), Ext::Zx8);
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true
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Emit::Native
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}
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PpcOpcode::lhz => {
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emit_load(ops, off, helpers.read_u16, ra, rd, instr.d(), Ext::Zx16);
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true
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Emit::Native
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}
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PpcOpcode::lha => {
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emit_load(ops, off, helpers.read_u16, ra, rd, instr.d(), Ext::Sx16);
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true
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Emit::Native
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}
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PpcOpcode::lwz => {
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emit_load(ops, off, helpers.read_u32, ra, rd, instr.d(), Ext::Zx32);
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true
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Emit::Native
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}
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// ===== Stores: mem[(rA==0?0:gpr[rA]) + EXTS(D/DS)] = gpr[rS] =====
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PpcOpcode::stb => {
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emit_store(ops, off, helpers.store_u8, ra, rd, instr.d());
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true
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Emit::Native
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}
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PpcOpcode::sth => {
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emit_store(ops, off, helpers.store_u16, ra, rd, instr.d());
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true
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Emit::Native
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}
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PpcOpcode::stw => {
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emit_store(ops, off, helpers.store_u32, ra, rd, instr.d());
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true
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Emit::Native
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}
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PpcOpcode::std => {
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// DS-form displacement (14-bit signed << 2).
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emit_store(ops, off, helpers.store_u64, ra, rd, instr.ds());
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true
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Emit::Native
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}
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_ => false,
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// ===== Branches (block terminators) =====
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// Unconditional: target = aa ? LI : pc+LI; lk -> lr = pc+4; pc = target.
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PpcOpcode::bx => {
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if instr.lk() {
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// lr = (pc+4) as u64, from the ORIGINAL pc (before it changes).
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dynasm!(ops ; .arch x64
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; mov edx, [r15 + off.pc]
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; lea ecx, [rdx + 4] // 64-bit base wraps like (pc+4) as u32
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; mov [r15 + off.lr], rcx
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);
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}
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if instr.aa() {
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let tgt = instr.li() as u32 as i32;
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dynasm!(ops ; .arch x64 ; mov DWORD [r15 + off.pc], tgt);
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} else {
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let li = instr.li(); // signed offset (already <<2)
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dynasm!(ops ; .arch x64 ; add DWORD [r15 + off.pc], li);
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}
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count_only(ops, off);
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Emit::Branch
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}
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// Conditional: optional CTR decrement + CTR/CR test; taken -> pc=target,
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// else pc+=4; lk -> lr = pc+4 in both cases (from the original pc).
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PpcOpcode::bcx => {
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let bo = instr.bo();
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let bi = instr.bi();
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emit_branch_cond(ops, off, bo, bi); // taken (0/1) -> al
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dynasm!(ops ; .arch x64 ; mov edx, [r15 + off.pc]); // edx = original pc
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if instr.lk() {
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dynasm!(ops ; .arch x64
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; lea ecx, [rdx + 4]
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; mov [r15 + off.lr], rcx
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);
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}
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// not-taken candidate (pc+4) in ecx; taken target in edx.
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dynasm!(ops ; .arch x64 ; lea ecx, [rdx + 4]);
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if instr.aa() {
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let tgt = instr.bd() as u32 as i32;
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dynasm!(ops ; .arch x64 ; mov edx, tgt);
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} else {
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let bd = instr.bd(); // signed offset (already <<2)
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dynasm!(ops ; .arch x64 ; lea edx, [rdx + bd]);
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}
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dynasm!(ops ; .arch x64
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; test al, al
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; cmovne ecx, edx // taken -> target, else stays pc+4
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; mov [r15 + off.pc], ecx
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);
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count_only(ops, off);
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Emit::Branch
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}
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// Return via LR: taken -> pc = (lr as u32) & !3, else pc+=4;
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// lk -> lr = pc+4 (set AFTER reading lr for the target).
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PpcOpcode::bclrx => {
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let bo = instr.bo();
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let bi = instr.bi();
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emit_branch_cond(ops, off, bo, bi); // taken (0/1) -> al
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dynasm!(ops ; .arch x64
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; mov edx, [r15 + off.pc]
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; lea r8d, [rdx + 4] // next_pc = pc+4, preserved in r8
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; mov edx, [r15 + off.lr] // edx = lr low 32
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; and edx, -4 // & !3
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; mov ecx, r8d // not-taken default = next_pc
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; test al, al
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; cmovne ecx, edx // taken -> lr & !3
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; mov [r15 + off.pc], ecx
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);
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if instr.lk() {
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dynasm!(ops ; .arch x64 ; mov [r15 + off.lr], r8);
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}
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count_only(ops, off);
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Emit::Branch
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}
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_ => Emit::Fallback,
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}
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}
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/// Emit the `bcx`/`bclrx` condition evaluation, leaving `taken` (0/1) in `al`.
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/// Mirrors the interpreter: optionally decrement CTR (when `BO2` is clear), then
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/// `ctr_ok = BO2 || (((ctr as u32)!=0) ^ BO3)` and
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/// `cond_ok = BO0 || (get_cr_bit(bi) == BO1)`; `taken = ctr_ok && cond_ok`.
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/// (`BO` bits are numbered from the MSB: BO0=0x10, BO1=0x08, BO2=0x04,
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/// BO3=0x02.) Everything folds to constants at compile time except the runtime
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/// CTR/CR reads. Clobbers rax, rcx.
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fn emit_branch_cond(ops: &mut Asm, off: &Offsets, bo: u32, bi: u32) {
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// ctr_ok -> al
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if bo & 0b00100 != 0 {
|
||||
dynasm!(ops ; .arch x64 ; mov al, 1); // CTR ignored: always ctr_ok
|
||||
} else {
|
||||
// Decrement CTR (u64), then test its low 32 bits against 0.
|
||||
dynasm!(ops ; .arch x64
|
||||
; dec QWORD [r15 + off.ctr]
|
||||
; mov ecx, [r15 + off.ctr]
|
||||
; test ecx, ecx
|
||||
);
|
||||
if bo & 0b00010 != 0 {
|
||||
dynasm!(ops ; .arch x64 ; sete al); // branch if CTR == 0
|
||||
} else {
|
||||
dynasm!(ops ; .arch x64 ; setne al); // branch if CTR != 0
|
||||
}
|
||||
}
|
||||
// cond_ok -> cl
|
||||
if bo & 0b10000 != 0 {
|
||||
dynasm!(ops ; .arch x64 ; mov cl, 1); // condition ignored: always cond_ok
|
||||
} else {
|
||||
let crbit = off.cr_bit_off(bi);
|
||||
dynasm!(ops ; .arch x64 ; mov cl, [r15 + crbit]); // crbit is 0/1
|
||||
if bo & 0b01000 == 0 {
|
||||
// expected bit == 0: cond_ok = !crbit
|
||||
dynasm!(ops ; .arch x64 ; xor cl, 1);
|
||||
}
|
||||
}
|
||||
dynasm!(ops ; .arch x64 ; and al, cl); // taken = ctr_ok & cond_ok
|
||||
}
|
||||
|
||||
/// Result-extension mode for a native load.
|
||||
#[derive(Clone, Copy)]
|
||||
enum Ext {
|
||||
|
||||
@@ -242,11 +242,24 @@ fn compile_block(block: &DecodedBlock) -> CompiledBlock {
|
||||
);
|
||||
|
||||
for instr in instrs.iter() {
|
||||
// Native fast path: emitters fully handle the instruction (compute +
|
||||
// pc+=4 + counter bumps) and never diverge control flow, so no exit
|
||||
// checks are needed after them.
|
||||
if emit::try_emit_native(&mut ops, &off, &mem_helpers, instr) {
|
||||
continue;
|
||||
match emit::try_emit_native(&mut ops, &off, &mem_helpers, instr) {
|
||||
// Native non-branch: fully handled (compute + pc+=4 + counter
|
||||
// bumps), control always continues — no exit check needed.
|
||||
emit::Emit::Native => continue,
|
||||
// Native branch: it set pc/lr/ctr + bumped counters. Append the same
|
||||
// pc-discontinuity check the fallback path uses so a taken branch
|
||||
// ends the block and a fall-through continues (matches step_block).
|
||||
emit::Emit::Branch => {
|
||||
let expected_next = instr.addr.wrapping_add(4) as i32;
|
||||
dynasm!(ops
|
||||
; .arch x64
|
||||
; cmp DWORD [r15 + off.pc], expected_next
|
||||
; jne =>l_cont
|
||||
);
|
||||
continue;
|
||||
}
|
||||
// Un-ported opcode: emit the interpreter fallback below.
|
||||
emit::Emit::Fallback => {}
|
||||
}
|
||||
// Interpreter fallback for un-ported opcodes.
|
||||
let instr_ptr = instr as *const DecodedInstr as usize as i64;
|
||||
|
||||
@@ -148,6 +148,20 @@ fn enc_x(op: u32, b6_10: u32, b11_15: u32, b16_20: u32, xo: u32, rc: u32) -> u32
|
||||
fn enc_xo(op: u32, b6_10: u32, b11_15: u32, b16_20: u32, oe: u32, xo: u32, rc: u32) -> u32 {
|
||||
(op << 26) | (b6_10 << 21) | (b11_15 << 16) | (b16_20 << 11) | (oe << 10) | (xo << 1) | rc
|
||||
}
|
||||
/// I-form `bx` (op 18): 24-bit LI (bits 6-29, target offset >> 2), AA, LK.
|
||||
fn enc_bx(off_bytes: i32, aa: u32, lk: u32) -> u32 {
|
||||
let li24 = ((off_bytes >> 2) as u32) & 0x00FF_FFFF;
|
||||
(18 << 26) | (li24 << 2) | (aa << 1) | lk
|
||||
}
|
||||
/// B-form `bcx` (op 16): BO, BI, 14-bit BD (bits 16-29, offset >> 2), AA, LK.
|
||||
fn enc_bcx(bo: u32, bi: u32, off_bytes: i32, aa: u32, lk: u32) -> u32 {
|
||||
let bd14 = ((off_bytes >> 2) as u32) & 0x0000_3FFF;
|
||||
(16 << 26) | (bo << 21) | (bi << 16) | (bd14 << 2) | (aa << 1) | lk
|
||||
}
|
||||
/// XL-form `bclrx` (op 19, XO 16): BO, BI, LK.
|
||||
fn enc_bclrx(bo: u32, bi: u32, lk: u32) -> u32 {
|
||||
(19 << 26) | (bo << 21) | (bi << 16) | (16 << 1) | lk
|
||||
}
|
||||
|
||||
/// Deterministic PRNG (splitmix64-ish) so failures are reproducible.
|
||||
fn rng(state: &mut u64) -> u64 {
|
||||
@@ -177,7 +191,7 @@ fn check(raw: u32, gpr: [u64; 32]) {
|
||||
let helpers = crate::MemHelpers::resolve();
|
||||
let mut probe = dynasmrt::x64::Assembler::new().unwrap();
|
||||
assert!(
|
||||
emit::try_emit_native(&mut probe, &off, &helpers, &instr),
|
||||
emit::try_emit_native(&mut probe, &off, &helpers, &instr) != emit::Emit::Fallback,
|
||||
"opcode not natively emitted for raw={raw:#010x} ({:?})",
|
||||
instr.opcode
|
||||
);
|
||||
@@ -224,7 +238,7 @@ fn check_cmp(raw: u32, gpr: [u64; 32], xer_so: u8) {
|
||||
let helpers = crate::MemHelpers::resolve();
|
||||
let mut probe = dynasmrt::x64::Assembler::new().unwrap();
|
||||
assert!(
|
||||
emit::try_emit_native(&mut probe, &off, &helpers, &instr),
|
||||
emit::try_emit_native(&mut probe, &off, &helpers, &instr) != emit::Emit::Fallback,
|
||||
"compare not natively emitted raw={raw:#010x} ({:?})",
|
||||
instr.opcode
|
||||
);
|
||||
@@ -358,6 +372,109 @@ fn compares_match() {
|
||||
}
|
||||
}
|
||||
|
||||
/// Branch differential check: seed pc/lr/ctr/cr identically, run the branch
|
||||
/// through the interpreter and the JIT (a 1-instruction block), and assert
|
||||
/// pc/lr/ctr/cr/counters/StepResult all match. Branches must be emitted as
|
||||
/// [`emit::Emit::Branch`] specifically.
|
||||
fn check_branch(raw: u32, lr: u64, ctr: u64, cr_seed: u8) {
|
||||
let pc = 0x8200_1000u32;
|
||||
let instr: DecodedInstr = decode(raw, pc);
|
||||
let off = emit::Offsets::resolve();
|
||||
let helpers = crate::MemHelpers::resolve();
|
||||
let mut probe = dynasmrt::x64::Assembler::new().unwrap();
|
||||
assert_eq!(
|
||||
emit::try_emit_native(&mut probe, &off, &helpers, &instr),
|
||||
emit::Emit::Branch,
|
||||
"branch not emitted as Emit::Branch raw={raw:#010x} ({:?})",
|
||||
instr.opcode
|
||||
);
|
||||
|
||||
let seed = |c: &mut PpcContext| {
|
||||
c.lr = lr;
|
||||
c.ctr = ctr;
|
||||
for (i, f) in c.cr.iter_mut().enumerate() {
|
||||
*f = xenia_cpu::context::CrField::from_u8(cr_seed.wrapping_add(i as u8) & 0xF);
|
||||
}
|
||||
};
|
||||
|
||||
let mem = NoMem;
|
||||
let mut a = ctx_from_gpr([0u64; 32], pc);
|
||||
seed(&mut a);
|
||||
let ra = interpret_one(&mut a, &mem, &instr);
|
||||
a.cycle_count += 1;
|
||||
a.timebase += 1;
|
||||
|
||||
let mut b = ctx_from_gpr([0u64; 32], pc);
|
||||
seed(&mut b);
|
||||
let block = DecodedBlock {
|
||||
start_pc: pc,
|
||||
end_pc: pc.wrapping_add(4),
|
||||
page_version: 0,
|
||||
instrs: vec![instr],
|
||||
sync_sensitive: false,
|
||||
};
|
||||
let cb: CompiledBlock = compile_block(&block);
|
||||
let rb = run_jit_block(&cb, &mut b, &mem);
|
||||
|
||||
assert_eq!(a.pc, b.pc, "pc mismatch raw={raw:#010x} ({:?})", instr.opcode);
|
||||
assert_eq!(a.lr, b.lr, "lr mismatch raw={raw:#010x} ({:?})", instr.opcode);
|
||||
assert_eq!(a.ctr, b.ctr, "ctr mismatch raw={raw:#010x} ({:?})", instr.opcode);
|
||||
assert_eq!(a.cycle_count, b.cycle_count, "cycle mismatch raw={raw:#010x}");
|
||||
assert_eq!(a.timebase, b.timebase, "timebase mismatch raw={raw:#010x}");
|
||||
let cra: [u8; 8] = std::array::from_fn(|i| a.cr[i].as_u8());
|
||||
let crb: [u8; 8] = std::array::from_fn(|i| b.cr[i].as_u8());
|
||||
assert_eq!(cra, crb, "cr mismatch raw={raw:#010x}");
|
||||
assert_eq!(ra, rb, "StepResult mismatch raw={raw:#010x}");
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn unconditional_branch_matches() {
|
||||
let mut s = 0xb00u64;
|
||||
for _ in 0..ITERS {
|
||||
// Non-negative and negative offsets (multiples of 4), both lk states.
|
||||
let off = ((rng(&mut s) & 0x3FFF) as i32) * 4 - 0x8000;
|
||||
for lk in [0u32, 1u32] {
|
||||
check_branch(enc_bx(off, 0, lk), 0xdead_beef_1234_0000, 0x55, 0);
|
||||
}
|
||||
// Absolute form: small positive absolute target.
|
||||
let abs = ((rng(&mut s) & 0x3FFF) as i32) * 4;
|
||||
check_branch(enc_bx(abs, 1, 0), 0, 0, 0);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn conditional_branch_matches() {
|
||||
let mut s = 0xbc0u64;
|
||||
for _ in 0..ITERS {
|
||||
let bo = (rng(&mut s) % 32) as u32; // exhaustive over the 5 BO bits
|
||||
let bi = (rng(&mut s) % 32) as u32; // any CR bit
|
||||
let off = ((rng(&mut s) & 0x1FFF) as i32) * 4 - 0x4000;
|
||||
let ctr = rng(&mut s); // hits ctr==1 boundary (dec ->0) sometimes
|
||||
let cr_seed = rng(&mut s) as u8;
|
||||
for lk in [0u32, 1u32] {
|
||||
check_branch(enc_bcx(bo, bi, off, 0, lk), 0, ctr, cr_seed);
|
||||
}
|
||||
// Force the CTR==1 -> 0 boundary explicitly.
|
||||
check_branch(enc_bcx(bo, bi, off, 0, 0), 0, 1, cr_seed);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn return_branch_matches() {
|
||||
let mut s = 0xb1cu64;
|
||||
for _ in 0..ITERS {
|
||||
let bo = (rng(&mut s) % 32) as u32;
|
||||
let bi = (rng(&mut s) % 32) as u32;
|
||||
let lr = rng(&mut s); // exercises the & !3 alignment mask
|
||||
let ctr = rng(&mut s);
|
||||
let cr_seed = rng(&mut s) as u8;
|
||||
for lk in [0u32, 1u32] {
|
||||
check_branch(enc_bclrx(bo, bi, lk), lr, ctr, cr_seed);
|
||||
}
|
||||
check_branch(enc_bclrx(bo, bi, 0), lr, 1, cr_seed);
|
||||
}
|
||||
}
|
||||
|
||||
/// The recording/OE forms and the db16cyc hint must NOT be natively emitted
|
||||
/// (they fall back to the interpreter). Guards against a future emitter
|
||||
/// accidentally handling a form it can't reproduce.
|
||||
@@ -375,7 +492,7 @@ fn recording_and_hint_forms_fall_back() {
|
||||
for raw in cases {
|
||||
let instr = decode(raw, 0x8200_1000);
|
||||
assert!(
|
||||
!emit::try_emit_native(&mut probe, &off, &helpers, &instr),
|
||||
emit::try_emit_native(&mut probe, &off, &helpers, &instr) == emit::Emit::Fallback,
|
||||
"raw={raw:#010x} ({:?}) should fall back, not native",
|
||||
instr.opcode
|
||||
);
|
||||
@@ -392,7 +509,7 @@ fn check_mem(raw: u32, gpr: [u64; 32]) {
|
||||
let helpers = crate::MemHelpers::resolve();
|
||||
let mut probe = dynasmrt::x64::Assembler::new().unwrap();
|
||||
assert!(
|
||||
emit::try_emit_native(&mut probe, &off, &helpers, &instr),
|
||||
emit::try_emit_native(&mut probe, &off, &helpers, &instr) != emit::Emit::Fallback,
|
||||
"mem opcode not natively emitted raw={raw:#010x} ({:?})",
|
||||
instr.opcode
|
||||
);
|
||||
|
||||
Reference in New Issue
Block a user