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chore: add migration/ bundle for cross-machine setup

Browse Source 
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
2026-05-10 21:38:38 +02:00
parent 8e709b0a24
commit e6d43a23ac
505 changed files with 86028 additions and 0 deletions
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# Form `A` — A — Arithmetic (three-source FPU)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (59 or 63) |
| 6–10 | `FRT` | destination FPR |
| 11–15 | `FRA` | source A FPR |
| 16–20 | `FRB` | source B FPR |
| 21–25 | `FRC` | source C FPR (multiplier for madd-style ops) |
| 26–30 | `XO` | extended opcode (5 bits) |
| 31 | `Rc` | record-form flag (updates CR1) |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`fdivsx`](../fpu/fdivsx.md) | `0xec000024` | fpu | Floating Divide Single |
| [`fsubsx`](../fpu/fsubsx.md) | `0xec000028` | fpu | Floating Subtract Single |
| [`faddsx`](../fpu/faddsx.md) | `0xec00002a` | fpu | Floating Add Single |
| [`fsqrtsx`](../fpu/fsqrtsx.md) | `0xec00002c` | fpu | Floating Square Root Single |
| [`fresx`](../fpu/fresx.md) | `0xec000030` | fpu | Floating Reciprocal Estimate Single |
| [`fmulsx`](../fpu/fmulsx.md) | `0xec000032` | fpu | Floating Multiply Single |
| [`fmsubsx`](../fpu/fmsubsx.md) | `0xec000038` | fpu | Floating Multiply-Subtract Single |
| [`fmaddsx`](../fpu/fmaddsx.md) | `0xec00003a` | fpu | Floating Multiply-Add Single |
| [`fnmsubsx`](../fpu/fnmsubsx.md) | `0xec00003c` | fpu | Floating Negative Multiply-Subtract Single |
| [`fnmaddsx`](../fpu/fnmaddsx.md) | `0xec00003e` | fpu | Floating Negative Multiply-Add Single |
| [`fdivx`](../fpu/fdivx.md) | `0xfc000024` | fpu | Floating Divide |
| [`fsubx`](../fpu/fsubx.md) | `0xfc000028` | fpu | Floating Subtract |
| [`faddx`](../fpu/faddx.md) | `0xfc00002a` | fpu | Floating Add |
| [`fsqrtx`](../fpu/fsqrtx.md) | `0xfc00002c` | fpu | Floating Square Root |
| [`fselx`](../fpu/fselx.md) | `0xfc00002e` | fpu | Floating Select |
| [`fmulx`](../fpu/fmulx.md) | `0xfc000032` | fpu | Floating Multiply |
| [`frsqrtex`](../fpu/frsqrtex.md) | `0xfc000034` | fpu | Floating Reciprocal Square Root Estimate |
| [`fmsubx`](../fpu/fmsubx.md) | `0xfc000038` | fpu | Floating Multiply-Subtract |
| [`fmaddx`](../fpu/fmaddx.md) | `0xfc00003a` | fpu | Floating Multiply-Add |
| [`fnmsubx`](../fpu/fnmsubx.md) | `0xfc00003c` | fpu | Floating Negative Multiply-Subtract |
| [`fnmaddx`](../fpu/fnmaddx.md) | `0xfc00003e` | fpu | Floating Negative Multiply-Add |
<!-- GENERATED: END -->

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# Form `B` — B — Conditional Branch
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `BO` | branch options |
| 11–15 | `BI` | CR bit to test |
| 16–29 | `BD` | signed 14-bit word-offset target |
| 30 | `AA` | absolute-address flag |
| 31 | `LK` | link flag |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`bcx`](../branch/bcx.md) | `0x40000000` | branch | Branch Conditional |
<!-- GENERATED: END -->

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# Form `D` — D — Displacement (load/store and immediate ALU)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS when storing) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`tdi`](../branch/tdi.md) | `0x08000000` | branch | Trap Doubleword Immediate |
| [`twi`](../branch/twi.md) | `0x0c000000` | branch | Trap Word Immediate |
| [`mulli`](../alu/mulli.md) | `0x1c000000` | integer | Multiply Low Immediate |
| [`subficx`](../alu/subficx.md) | `0x20000000` | integer | Subtract From Immediate Carrying |
| [`cmpli`](../alu/cmpli.md) | `0x28000000` | integer | Compare Logical Immediate |
| [`cmpi`](../alu/cmpi.md) | `0x2c000000` | integer | Compare Immediate |
| [`addic`](../alu/addic.md) | `0x30000000` | integer | Add Immediate Carrying |
| [`addic.`](../alu/addicx.md) | `0x34000000` | integer | Add Immediate Carrying and Record |
| [`addi`](../alu/addi.md) | `0x38000000` | integer | Add Immediate |
| [`addis`](../alu/addis.md) | `0x3c000000` | integer | Add Immediate Shifted |
| [`ori`](../alu/ori.md) | `0x60000000` | integer | OR Immediate |
| [`oris`](../alu/oris.md) | `0x64000000` | integer | OR Immediate Shifted |
| [`xori`](../alu/xori.md) | `0x68000000` | integer | XOR Immediate |
| [`xoris`](../alu/xoris.md) | `0x6c000000` | integer | XOR Immediate Shifted |
| [`andi.`](../alu/andix.md) | `0x70000000` | integer | AND Immediate |
| [`andis.`](../alu/andisx.md) | `0x74000000` | integer | AND Immediate Shifted |
| [`lwz`](../memory/lwz.md) | `0x80000000` | memory | Load Word and Zero |
| [`lwzu`](../memory/lwz.md) | `0x84000000` | memory | Load Word and Zero with Update |
| [`lbz`](../memory/lbz.md) | `0x88000000` | memory | Load Byte and Zero |
| [`lbzu`](../memory/lbz.md) | `0x8c000000` | memory | Load Byte and Zero with Update |
| [`stw`](../memory/stw.md) | `0x90000000` | memory | Store Word |
| [`stwu`](../memory/stw.md) | `0x94000000` | memory | Store Word with Update |
| [`stb`](../memory/stb.md) | `0x98000000` | memory | Store Byte |
| [`stbu`](../memory/stb.md) | `0x9c000000` | memory | Store Byte with Update |
| [`lhz`](../memory/lhz.md) | `0xa0000000` | memory | Load Half Word and Zero |
| [`lhzu`](../memory/lhz.md) | `0xa4000000` | memory | Load Half Word and Zero with Update |
| [`lha`](../memory/lha.md) | `0xa8000000` | memory | Load Half Word Algebraic |
| [`lhau`](../memory/lha.md) | `0xac000000` | memory | Load Half Word Algebraic with Update |
| [`sth`](../memory/sth.md) | `0xb0000000` | memory | Store Half Word |
| [`sthu`](../memory/sth.md) | `0xb4000000` | memory | Store Half Word with Update |
| [`lmw`](../memory/lmw.md) | `0xb8000000` | memory | Load Multiple Word |
| [`stmw`](../memory/stmw.md) | `0xbc000000` | memory | Store Multiple Word |
| [`lfs`](../memory/lfs.md) | `0xc0000000` | memory | Load Floating-Point Single |
| [`lfsu`](../memory/lfs.md) | `0xc4000000` | memory | Load Floating-Point Single with Update |
| [`lfd`](../memory/lfd.md) | `0xc8000000` | memory | Load Floating-Point Double |
| [`lfdu`](../memory/lfd.md) | `0xcc000000` | memory | Load Floating-Point Double with Update |
| [`stfs`](../memory/stfs.md) | `0xd0000000` | memory | Store Floating-Point Single |
| [`stfsu`](../memory/stfs.md) | `0xd4000000` | memory | Store Floating-Point Single with Update |
| [`stfd`](../memory/stfd.md) | `0xd8000000` | memory | Store Floating-Point Double |
| [`stfdu`](../memory/stfd.md) | `0xdc000000` | memory | Store Floating-Point Double with Update |
<!-- GENERATED: END -->

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# Form `DCBZ` — DCBZ — Cache Block Zeroing (special X variant)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (31) |
| 6–10 | `—` | reserved |
| 11–15 | `RA` | base register (0 ⇒ literal 0) |
| 16–20 | `RB` | offset register |
| 21–30 | `XO` | extended opcode (1014 for dcbz / 1010 for dcbz128) |
| 31 | `—` | reserved |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`dcbz`](../memory/dcbz.md) | `0x7c0007ec` | memory | Data Cache Block Clear to Zero |
| [`dcbz128`](../memory/dcbz.md) | `0x7c2007ec` | memory | Data Cache Block Clear to Zero 128 |
<!-- GENERATED: END -->

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# Form `DS` — DS — Doubleword Shift (word-scaled displacement)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0) |
| 16–29 | `DS` | 14-bit signed word-scaled displacement |
| 30–31 | `XO` | extended opcode |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`ld`](../memory/ld.md) | `0xe8000000` | memory | Load Doubleword |
| [`ldu`](../memory/ld.md) | `0xe8000001` | memory | Load Doubleword with Update |
| [`lwa`](../memory/lwa.md) | `0xe8000002` | memory | Load Word Algebraic |
| [`std`](../memory/std.md) | `0xf8000000` | memory | Store Doubleword |
| [`stdu`](../memory/std.md) | `0xf8000001` | memory | Store Doubleword with Update |
<!-- GENERATED: END -->

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# Form `I` — I — Immediate Branch
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–29 | `LI` | signed 24-bit word-offset target |
| 30 | `AA` | absolute-address flag |
| 31 | `LK` | link flag (bl/ba/bla) |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`bx`](../branch/bx.md) | `0x48000000` | branch | Branch |
<!-- GENERATED: END -->

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# Form `M` — M — Mask (rlwinm/rlwimi/rlwnm)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RS` | source GPR |
| 11–15 | `RA` | destination GPR |
| 16–20 | `SH/RB` | shift amount or source B |
| 21–25 | `MB` | mask begin |
| 26–30 | `ME` | mask end |
| 31 | `Rc` | record-form flag |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`rlwimix`](../alu/rlwimix.md) | `0x50000000` | integer | Rotate Left Word Immediate then Mask Insert |
| [`rlwinmx`](../alu/rlwinmx.md) | `0x54000000` | integer | Rotate Left Word Immediate then AND with Mask |
| [`rlwnmx`](../alu/rlwnmx.md) | `0x5c000000` | integer | Rotate Left Word then AND with Mask |
<!-- GENERATED: END -->

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# Form `MD` — MD — Mask Double (rldicr/rldicl/rldic/rldimi)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (30) |
| 6–10 | `RS` | source GPR |
| 11–15 | `RA` | destination GPR |
| 16–20 | `sh` | shift amount low 5 bits |
| 21–26 | `mb/me` | 6-bit mask field (swapped halves) |
| 27–29 | `XO` | extended opcode |
| 30 | `sh5` | shift amount high bit |
| 31 | `Rc` | record-form flag |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`rldiclx`](../alu/rldiclx.md) | `0x78000000` | integer | Rotate Left Doubleword Immediate then Clear Left |
| [`rldicrx`](../alu/rldicrx.md) | `0x78000004` | integer | Rotate Left Doubleword Immediate then Clear Right |
| [`rldicx`](../alu/rldicx.md) | `0x78000008` | integer | Rotate Left Doubleword Immediate then Clear |
| [`rldimix`](../alu/rldimix.md) | `0x7800000c` | integer | Rotate Left Doubleword Immediate then Mask Insert |
<!-- GENERATED: END -->

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# Form `MDS` — MDS — Mask Double, Shift-by-register (rldcl/rldcr)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (30) |
| 6–10 | `RS` | source GPR |
| 11–15 | `RA` | destination GPR |
| 16–20 | `RB` | source B GPR |
| 21–26 | `mb/me` | 6-bit mask field (swapped halves) |
| 27–30 | `XO` | extended opcode |
| 31 | `Rc` | record-form flag |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`rldclx`](../alu/rldclx.md) | `0x78000010` | integer | Rotate Left Doubleword then Clear Left |
| [`rldcrx`](../alu/rldcrx.md) | `0x78000012` | integer | Rotate Left Doubleword then Clear Right |
<!-- GENERATED: END -->

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# Form `SC` — SC — System Call
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (17) |
| 6–19 | `—` | reserved |
| 20–26 | `LEV` | exception level |
| 27–29 | `—` | reserved |
| 30 | `1` | fixed 1 |
| 31 | `—` | reserved |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`sc`](../branch/sc.md) | `0x44000002` | branch | System Call |
<!-- GENERATED: END -->

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# Form `VA` — VA — Vector Arithmetic (4-operand, madd-style)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21–25 | `VRC` | source C / shift |
| 26–31 | `XO` | extended opcode (6 bits) |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vmhaddshs`](../vmx/vmhaddshs.md) | `0x10000020` | vmx | Vector Multiply-High and Add Signed Signed Half Word Saturate |
| [`vmhraddshs`](../vmx/vmhraddshs.md) | `0x10000021` | vmx | Vector Multiply-High Round and Add Signed Signed Half Word Saturate |
| [`vmladduhm`](../vmx/vmladduhm.md) | `0x10000022` | vmx | Vector Multiply-Low and Add Unsigned Half Word Modulo |
| [`vmsumubm`](../vmx/vmsumubm.md) | `0x10000024` | vmx | Vector Multiply-Sum Unsigned Byte Modulo |
| [`vmsummbm`](../vmx/vmsummbm.md) | `0x10000025` | vmx | Vector Multiply-Sum Mixed-Sign Byte Modulo |
| [`vmsumuhm`](../vmx/vmsumuhm.md) | `0x10000026` | vmx | Vector Multiply-Sum Unsigned Half Word Modulo |
| [`vmsumuhs`](../vmx/vmsumuhs.md) | `0x10000027` | vmx | Vector Multiply-Sum Unsigned Half Word Saturate |
| [`vmsumshm`](../vmx/vmsumshm.md) | `0x10000028` | vmx | Vector Multiply-Sum Signed Half Word Modulo |
| [`vmsumshs`](../vmx/vmsumshs.md) | `0x10000029` | vmx | Vector Multiply-Sum Signed Half Word Saturate |
| [`vsel`](../vmx/vsel.md) | `0x1000002a` | vmx | Vector Conditional Select |
| [`vperm`](../vmx/vperm.md) | `0x1000002b` | vmx | Vector Permute |
| [`vsldoi`](../vmx/vsldoi.md) | `0x1000002c` | vmx | Vector Shift Left Double by Octet Immediate |
| [`vmaddfp`](../vmx/vmaddfp.md) | `0x1000002e` | vmx | Vector Multiply-Add Floating Point |
| [`vnmsubfp`](../vmx/vnmsubfp.md) | `0x1000002f` | vmx | Vector Negative Multiply-Subtract Floating Point |
<!-- GENERATED: END -->

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# Form `VC` — VC — Vector Compare (with Rc → CR6)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21 | `Rc` | record-form flag (updates CR6) |
| 22–31 | `XO` | extended opcode (10 bits) |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vcmpequb`](../vmx/vcmpequb.md) | `0x10000006` | vmx | Vector Compare Equal-to Unsigned Byte |
| [`vcmpequh`](../vmx/vcmpequh.md) | `0x10000046` | vmx | Vector Compare Equal-to Unsigned Half Word |
| [`vcmpequw`](../vmx/vcmpequw.md) | `0x10000086` | vmx | Vector Compare Equal-to Unsigned Word |
| [`vcmpeqfp`](../vmx/vcmpeqfp.md) | `0x100000c6` | vmx | Vector Compare Equal-to Floating Point |
| [`vcmpgefp`](../vmx/vcmpgefp.md) | `0x100001c6` | vmx | Vector Compare Greater-Than-or-Equal-to Floating Point |
| [`vcmpgtub`](../vmx/vcmpgtub.md) | `0x10000206` | vmx | Vector Compare Greater-Than Unsigned Byte |
| [`vcmpgtuh`](../vmx/vcmpgtuh.md) | `0x10000246` | vmx | Vector Compare Greater-Than Unsigned Half Word |
| [`vcmpgtuw`](../vmx/vcmpgtuw.md) | `0x10000286` | vmx | Vector Compare Greater-Than Unsigned Word |
| [`vcmpgtfp`](../vmx/vcmpgtfp.md) | `0x100002c6` | vmx | Vector Compare Greater-Than Floating Point |
| [`vcmpgtsb`](../vmx/vcmpgtsb.md) | `0x10000306` | vmx | Vector Compare Greater-Than Signed Byte |
| [`vcmpgtsh`](../vmx/vcmpgtsh.md) | `0x10000346` | vmx | Vector Compare Greater-Than Signed Half Word |
| [`vcmpgtsw`](../vmx/vcmpgtsw.md) | `0x10000386` | vmx | Vector Compare Greater-Than Signed Word |
| [`vcmpbfp`](../vmx/vcmpbfp.md) | `0x100003c6` | vmx | Vector Compare Bounds Floating Point |
<!-- GENERATED: END -->

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# Form `VX` — VX — Vector (3-operand Altivec)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vaddubm`](../vmx/vaddubm.md) | `0x10000000` | vmx | Vector Add Unsigned Byte Modulo |
| [`vmaxub`](../vmx/vmaxub.md) | `0x10000002` | vmx | Vector Maximum Unsigned Byte |
| [`vrlb`](../vmx/vrlb.md) | `0x10000004` | vmx | Vector Rotate Left Integer Byte |
| [`vmuloub`](../vmx/vmuloub.md) | `0x10000008` | vmx | Vector Multiply Odd Unsigned Byte |
| [`vaddfp`](../vmx/vaddfp.md) | `0x1000000a` | vmx | Vector Add Floating Point |
| [`vmrghb`](../vmx/vmrghb.md) | `0x1000000c` | vmx | Vector Merge High Byte |
| [`vpkuhum`](../vmx/vpkuhum.md) | `0x1000000e` | vmx | Vector Pack Unsigned Half Word Unsigned Modulo |
| [`vadduhm`](../vmx/vadduhm.md) | `0x10000040` | vmx | Vector Add Unsigned Half Word Modulo |
| [`vmaxuh`](../vmx/vmaxuh.md) | `0x10000042` | vmx | Vector Maximum Unsigned Half Word |
| [`vrlh`](../vmx/vrlh.md) | `0x10000044` | vmx | Vector Rotate Left Integer Half Word |
| [`vmulouh`](../vmx/vmulouh.md) | `0x10000048` | vmx | Vector Multiply Odd Unsigned Half Word |
| [`vsubfp`](../vmx/vsubfp.md) | `0x1000004a` | vmx | Vector Subtract Floating Point |
| [`vmrghh`](../vmx/vmrghh.md) | `0x1000004c` | vmx | Vector Merge High Half Word |
| [`vpkuwum`](../vmx/vpkuwum.md) | `0x1000004e` | vmx | Vector Pack Unsigned Word Unsigned Modulo |
| [`vadduwm`](../vmx/vadduwm.md) | `0x10000080` | vmx | Vector Add Unsigned Word Modulo |
| [`vmaxuw`](../vmx/vmaxuw.md) | `0x10000082` | vmx | Vector Maximum Unsigned Word |
| [`vrlw`](../vmx/vrlw.md) | `0x10000084` | vmx | Vector Rotate Left Integer Word |
| [`vmrghw`](../vmx/vmrghw.md) | `0x1000008c` | vmx | Vector Merge High Word |
| [`vpkuhus`](../vmx/vpkuhus.md) | `0x1000008e` | vmx | Vector Pack Unsigned Half Word Unsigned Saturate |
| [`vpkuwus`](../vmx/vpkuwus.md) | `0x100000ce` | vmx | Vector Pack Unsigned Word Unsigned Saturate |
| [`vmaxsb`](../vmx/vmaxsb.md) | `0x10000102` | vmx | Vector Maximum Signed Byte |
| [`vslb`](../vmx/vslb.md) | `0x10000104` | vmx | Vector Shift Left Integer Byte |
| [`vmulosb`](../vmx/vmulosb.md) | `0x10000108` | vmx | Vector Multiply Odd Signed Byte |
| [`vrefp`](../vmx/vrefp.md) | `0x1000010a` | vmx | Vector Reciprocal Estimate Floating Point |
| [`vmrglb`](../vmx/vmrglb.md) | `0x1000010c` | vmx | Vector Merge Low Byte |
| [`vpkshus`](../vmx/vpkshus.md) | `0x1000010e` | vmx | Vector Pack Signed Half Word Unsigned Saturate |
| [`vmaxsh`](../vmx/vmaxsh.md) | `0x10000142` | vmx | Vector Maximum Signed Half Word |
| [`vslh`](../vmx/vslh.md) | `0x10000144` | vmx | Vector Shift Left Integer Half Word |
| [`vmulosh`](../vmx/vmulosh.md) | `0x10000148` | vmx | Vector Multiply Odd Signed Half Word |
| [`vrsqrtefp`](../vmx/vrsqrtefp.md) | `0x1000014a` | vmx | Vector Reciprocal Square Root Estimate Floating Point |
| [`vmrglh`](../vmx/vmrglh.md) | `0x1000014c` | vmx | Vector Merge Low Half Word |
| [`vpkswus`](../vmx/vpkswus.md) | `0x1000014e` | vmx | Vector Pack Signed Word Unsigned Saturate |
| [`vaddcuw`](../vmx/vaddcuw.md) | `0x10000180` | vmx | Vector Add Carryout Unsigned Word |
| [`vmaxsw`](../vmx/vmaxsw.md) | `0x10000182` | vmx | Vector Maximum Signed Word |
| [`vslw`](../vmx/vslw.md) | `0x10000184` | vmx | Vector Shift Left Integer Word |
| [`vexptefp`](../vmx/vexptefp.md) | `0x1000018a` | vmx | Vector 2 Raised to the Exponent Estimate Floating Point |
| [`vmrglw`](../vmx/vmrglw.md) | `0x1000018c` | vmx | Vector Merge Low Word |
| [`vpkshss`](../vmx/vpkshss.md) | `0x1000018e` | vmx | Vector Pack Signed Half Word Signed Saturate |
| [`vsl`](../vmx/vsl.md) | `0x100001c4` | vmx | Vector Shift Left |
| [`vlogefp`](../vmx/vlogefp.md) | `0x100001ca` | vmx | Vector Log2 Estimate Floating Point |
| [`vpkswss`](../vmx/vpkswss.md) | `0x100001ce` | vmx | Vector Pack Signed Word Signed Saturate |
| [`vaddubs`](../vmx/vaddubs.md) | `0x10000200` | vmx | Vector Add Unsigned Byte Saturate |
| [`vminub`](../vmx/vminub.md) | `0x10000202` | vmx | Vector Minimum Unsigned Byte |
| [`vsrb`](../vmx/vsrb.md) | `0x10000204` | vmx | Vector Shift Right Byte |
| [`vmuleub`](../vmx/vmuleub.md) | `0x10000208` | vmx | Vector Multiply Even Unsigned Byte |
| [`vrfin`](../vmx/vrfin.md) | `0x1000020a` | vmx | Vector Round to Floating-Point Integer Nearest |
| [`vspltb`](../vmx/vspltb.md) | `0x1000020c` | vmx | Vector Splat Byte |
| [`vupkhsb`](../vmx/vupkhsb.md) | `0x1000020e` | vmx | Vector Unpack High Signed Byte |
| [`vadduhs`](../vmx/vadduhs.md) | `0x10000240` | vmx | Vector Add Unsigned Half Word Saturate |
| [`vminuh`](../vmx/vminuh.md) | `0x10000242` | vmx | Vector Minimum Unsigned Half Word |
| [`vsrh`](../vmx/vsrh.md) | `0x10000244` | vmx | Vector Shift Right Half Word |
| [`vmuleuh`](../vmx/vmuleuh.md) | `0x10000248` | vmx | Vector Multiply Even Unsigned Half Word |
| [`vrfiz`](../vmx/vrfiz.md) | `0x1000024a` | vmx | Vector Round to Floating-Point Integer toward Zero |
| [`vsplth`](../vmx/vsplth.md) | `0x1000024c` | vmx | Vector Splat Half Word |
| [`vupkhsh`](../vmx/vupkhsh.md) | `0x1000024e` | vmx | Vector Unpack High Signed Half Word |
| [`vadduws`](../vmx/vadduws.md) | `0x10000280` | vmx | Vector Add Unsigned Word Saturate |
| [`vminuw`](../vmx/vminuw.md) | `0x10000282` | vmx | Vector Minimum Unsigned Word |
| [`vsrw`](../vmx/vsrw.md) | `0x10000284` | vmx | Vector Shift Right Word |
| [`vrfip`](../vmx/vrfip.md) | `0x1000028a` | vmx | Vector Round to Floating-Point Integer toward +Infinity |
| [`vspltw`](../vmx/vspltw.md) | `0x1000028c` | vmx | Vector Splat Word |
| [`vupklsb`](../vmx/vupklsb.md) | `0x1000028e` | vmx | Vector Unpack Low Signed Byte |
| [`vsr`](../vmx/vsr.md) | `0x100002c4` | vmx | Vector Shift Right |
| [`vrfim`](../vmx/vrfim.md) | `0x100002ca` | vmx | Vector Round to Floating-Point Integer toward -Infinity |
| [`vupklsh`](../vmx/vupklsh.md) | `0x100002ce` | vmx | Vector Unpack Low Signed Half Word |
| [`vaddsbs`](../vmx/vaddsbs.md) | `0x10000300` | vmx | Vector Add Signed Byte Saturate |
| [`vminsb`](../vmx/vminsb.md) | `0x10000302` | vmx | Vector Minimum Signed Byte |
| [`vsrab`](../vmx/vsrab.md) | `0x10000304` | vmx | Vector Shift Right Algebraic Byte |
| [`vmulesb`](../vmx/vmulesb.md) | `0x10000308` | vmx | Vector Multiply Even Signed Byte |
| [`vcfux`](../vmx/vcfux.md) | `0x1000030a` | vmx | Vector Convert from Unsigned Fixed-Point Word |
| [`vspltisb`](../vmx/vspltisb.md) | `0x1000030c` | vmx | Vector Splat Immediate Signed Byte |
| [`vpkpx`](../vmx/vpkpx.md) | `0x1000030e` | vmx | Vector Pack Pixel |
| [`vaddshs`](../vmx/vaddshs.md) | `0x10000340` | vmx | Vector Add Signed Half Word Saturate |
| [`vminsh`](../vmx/vminsh.md) | `0x10000342` | vmx | Vector Minimum Signed Half Word |
| [`vsrah`](../vmx/vsrah.md) | `0x10000344` | vmx | Vector Shift Right Algebraic Half Word |
| [`vmulesh`](../vmx/vmulesh.md) | `0x10000348` | vmx | Vector Multiply Even Signed Half Word |
| [`vcfsx`](../vmx/vcfsx.md) | `0x1000034a` | vmx | Vector Convert from Signed Fixed-Point Word |
| [`vspltish`](../vmx/vspltish.md) | `0x1000034c` | vmx | Vector Splat Immediate Signed Half Word |
| [`vupkhpx`](../vmx/vupkhpx.md) | `0x1000034e` | vmx | Vector Unpack High Pixel |
| [`vaddsws`](../vmx/vaddsws.md) | `0x10000380` | vmx | Vector Add Signed Word Saturate |
| [`vminsw`](../vmx/vminsw.md) | `0x10000382` | vmx | Vector Minimum Signed Word |
| [`vsraw`](../vmx/vsraw.md) | `0x10000384` | vmx | Vector Shift Right Algebraic Word |
| [`vctuxs`](../vmx/vctuxs.md) | `0x1000038a` | vmx | Vector Convert to Unsigned Fixed-Point Word Saturate |
| [`vspltisw`](../vmx/vspltisw.md) | `0x1000038c` | vmx | Vector Splat Immediate Signed Word |
| [`vctsxs`](../vmx/vctsxs.md) | `0x100003ca` | vmx | Vector Convert to Signed Fixed-Point Word Saturate |
| [`vupklpx`](../vmx/vupklpx.md) | `0x100003ce` | vmx | Vector Unpack Low Pixel |
| [`vsububm`](../vmx/vsububm.md) | `0x10000400` | vmx | Vector Subtract Unsigned Byte Modulo |
| [`vavgub`](../vmx/vavgub.md) | `0x10000402` | vmx | Vector Average Unsigned Byte |
| [`vand`](../vmx/vand.md) | `0x10000404` | vmx | Vector Logical AND |
| [`vmaxfp`](../vmx/vmaxfp.md) | `0x1000040a` | vmx | Vector Maximum Floating Point |
| [`vslo`](../vmx/vslo.md) | `0x1000040c` | vmx | Vector Shift Left by Octet |
| [`vsubuhm`](../vmx/vsubuhm.md) | `0x10000440` | vmx | Vector Subtract Unsigned Half Word Modulo |
| [`vavguh`](../vmx/vavguh.md) | `0x10000442` | vmx | Vector Average Unsigned Half Word |
| [`vandc`](../vmx/vandc.md) | `0x10000444` | vmx | Vector Logical AND with Complement |
| [`vminfp`](../vmx/vminfp.md) | `0x1000044a` | vmx | Vector Minimum Floating Point |
| [`vsro`](../vmx/vsro.md) | `0x1000044c` | vmx | Vector Shift Right Octet |
| [`vsubuwm`](../vmx/vsubuwm.md) | `0x10000480` | vmx | Vector Subtract Unsigned Word Modulo |
| [`vavguw`](../vmx/vavguw.md) | `0x10000482` | vmx | Vector Average Unsigned Word |
| [`vor`](../vmx/vor.md) | `0x10000484` | vmx | Vector Logical OR |
| [`vxor`](../vmx/vxor.md) | `0x100004c4` | vmx | Vector Logical XOR |
| [`vavgsb`](../vmx/vavgsb.md) | `0x10000502` | vmx | Vector Average Signed Byte |
| [`vnor`](../vmx/vnor.md) | `0x10000504` | vmx | Vector Logical NOR |
| [`vavgsh`](../vmx/vavgsh.md) | `0x10000542` | vmx | Vector Average Signed Half Word |
| [`vsubcuw`](../vmx/vsubcuw.md) | `0x10000580` | vmx | Vector Subtract Carryout Unsigned Word |
| [`vavgsw`](../vmx/vavgsw.md) | `0x10000582` | vmx | Vector Average Signed Word |
| [`vsububs`](../vmx/vsububs.md) | `0x10000600` | vmx | Vector Subtract Unsigned Byte Saturate |
| [`mfvscr`](../control/mfvscr.md) | `0x10000604` | control | Move from VSCR |
| [`vsum4ubs`](../vmx/vsum4ubs.md) | `0x10000608` | vmx | Vector Sum Across Partial (1/4) Unsigned Byte Saturate |
| [`vsubuhs`](../vmx/vsubuhs.md) | `0x10000640` | vmx | Vector Subtract Unsigned Half Word Saturate |
| [`mtvscr`](../control/mtvscr.md) | `0x10000644` | control | Move to VSCR |
| [`vsum4shs`](../vmx/vsum4shs.md) | `0x10000648` | vmx | Vector Sum Across Partial (1/4) Signed Half Word Saturate |
| [`vsubuws`](../vmx/vsubuws.md) | `0x10000680` | vmx | Vector Subtract Unsigned Word Saturate |
| [`vsum2sws`](../vmx/vsum2sws.md) | `0x10000688` | vmx | Vector Sum Across Partial (1/2) Signed Word Saturate |
| [`vsubsbs`](../vmx/vsubsbs.md) | `0x10000700` | vmx | Vector Subtract Signed Byte Saturate |
| [`vsum4sbs`](../vmx/vsum4sbs.md) | `0x10000708` | vmx | Vector Sum Across Partial (1/4) Signed Byte Saturate |
| [`vsubshs`](../vmx/vsubshs.md) | `0x10000740` | vmx | Vector Subtract Signed Half Word Saturate |
| [`vsubsws`](../vmx/vsubsws.md) | `0x10000780` | vmx | Vector Subtract Signed Word Saturate |
| [`vsumsws`](../vmx/vsumsws.md) | `0x10000788` | vmx | Vector Sum Across Signed Word Saturate |
<!-- GENERATED: END -->

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# Form `VX128` — VX128 — VMX128 3-operand (register-fused)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4 or 5) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22 | `—` | reserved |
| 23–25 | `VC` | optional VC / XO sub-field |
| 26 | `VA128h` | source A middle bit |
| 27 | `—` | reserved |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vaddfp128`](../vmx128/vaddfp.md) | `0x14000010` | vmx | Vector128 Add Floating Point |
| [`vsubfp128`](../vmx128/vsubfp.md) | `0x14000050` | vmx | Vector128 Subtract Floating Point |
| [`vmulfp128`](../vmx128/vmulfp128.md) | `0x14000090` | vmx | Vector128 Multiply Floating-Point |
| [`vmaddfp128`](../vmx128/vmaddfp.md) | `0x140000d0` | vmx | Vector128 Multiply Add Floating Point |
| [`vmaddcfp128`](../vmx128/vmaddcfp128.md) | `0x14000110` | vmx | Vector128 Multiply Add Floating Point |
| [`vnmsubfp128`](../vmx128/vnmsubfp.md) | `0x14000150` | vmx | Vector128 Negative Multiply-Subtract Floating Point |
| [`vmsum3fp128`](../vmx128/vmsum3fp128.md) | `0x14000190` | vmx | Vector128 Multiply Sum 3-way Floating Point |
| [`vmsum4fp128`](../vmx128/vmsum4fp128.md) | `0x140001d0` | vmx | Vector128 Multiply Sum 4-way Floating-Point |
| [`vpkshss128`](../vmx128/vpkshss.md) | `0x14000200` | vmx | Vector128 Pack Signed Half Word Signed Saturate |
| [`vand128`](../vmx128/vand.md) | `0x14000210` | vmx | Vector128 Logical AND |
| [`vpkshus128`](../vmx128/vpkshus.md) | `0x14000240` | vmx | Vector128 Pack Signed Half Word Unsigned Saturate |
| [`vandc128`](../vmx128/vandc.md) | `0x14000250` | vmx | Vector128 Logical AND with Complement |
| [`vpkswss128`](../vmx128/vpkswss.md) | `0x14000280` | vmx | Vector128 Pack Signed Word Signed Saturate |
| [`vnor128`](../vmx128/vnor.md) | `0x14000290` | vmx | Vector128 Logical NOR |
| [`vpkswus128`](../vmx128/vpkswus.md) | `0x140002c0` | vmx | Vector128 Pack Signed Word Unsigned Saturate |
| [`vor128`](../vmx128/vor.md) | `0x140002d0` | vmx | Vector128 Logical OR |
| [`vpkuhum128`](../vmx128/vpkuhum.md) | `0x14000300` | vmx | Vector128 Pack Unsigned Half Word Unsigned Modulo |
| [`vxor128`](../vmx128/vxor.md) | `0x14000310` | vmx | Vector128 Logical XOR |
| [`vpkuhus128`](../vmx128/vpkuhus.md) | `0x14000340` | vmx | Vector128 Pack Unsigned Half Word Unsigned Saturate |
| [`vsel128`](../vmx128/vsel.md) | `0x14000350` | vmx | Vector128 Conditional Select |
| [`vpkuwum128`](../vmx128/vpkuwum.md) | `0x14000380` | vmx | Vector128 Pack Unsigned Word Unsigned Modulo |
| [`vslo128`](../vmx128/vslo.md) | `0x14000390` | vmx | Vector128 Shift Left Octet |
| [`vpkuwus128`](../vmx128/vpkuwus.md) | `0x140003c0` | vmx | Vector128 Pack Unsigned Word Unsigned Saturate |
| [`vsro128`](../vmx128/vsro.md) | `0x140003d0` | vmx | Vector128 Shift Right Octet |
| [`vrlw128`](../vmx128/vrlw.md) | `0x18000050` | vmx | Vector128 Rotate Left Word |
| [`vslw128`](../vmx128/vslw.md) | `0x180000d0` | vmx | Vector128 Shift Left Integer Word |
| [`vsraw128`](../vmx128/vsraw.md) | `0x18000150` | vmx | Vector128 Shift Right Arithmetic Word |
| [`vsrw128`](../vmx128/vsrw.md) | `0x180001d0` | vmx | Vector128 Shift Right Word |
| [`vmaxfp128`](../vmx128/vmaxfp.md) | `0x18000280` | vmx | Vector128 Maximum Floating Point |
| [`vminfp128`](../vmx128/vminfp.md) | `0x180002c0` | vmx | Vector128 Minimum Floating Point |
| [`vmrghw128`](../vmx128/vmrghw.md) | `0x18000300` | vmx | Vector128 Merge High Word |
| [`vmrglw128`](../vmx128/vmrglw.md) | `0x18000340` | vmx | Vector128 Merge Low Word |
| [`vupkhsb128`](../vmx128/vupkhsb.md) | `0x18000380` | vmx | Vector128 Unpack High Signed Byte |
| [`vupklsb128`](../vmx128/vupklsb.md) | `0x180003c0` | vmx | Vector128 Unpack Low Signed Byte |
<!-- GENERATED: END -->

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# Form `VX128_1` — VX128_1 — VMX128 vector load/store
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `RA` | address register |
| 16–20 | `RB` | offset register |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `—` | reserved |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`lvsl128`](../vmx128/lvsl.md) | `0x10000003` | vmx | Load Vector for Shift Left Indexed 128 |
| [`lvsr128`](../vmx128/lvsr.md) | `0x10000043` | vmx | Load Vector for Shift Right Indexed 128 |
| [`lvewx128`](../memory/lvewx.md) | `0x10000083` | memory | Load Vector Element Word Indexed 128 |
| [`lvx128`](../memory/lvx.md) | `0x100000c3` | memory | Load Vector Indexed 128 |
| [`stvewx128`](../memory/stvewx.md) | `0x10000183` | memory | Store Vector Element Word Indexed 128 |
| [`stvx128`](../memory/stvx.md) | `0x100001c3` | memory | Store Vector Indexed 128 |
| [`lvxl128`](../memory/lvxl.md) | `0x100002c3` | memory | Load Vector Indexed LRU 128 |
| [`stvxl128`](../memory/stvxl.md) | `0x100003c3` | memory | Store Vector Indexed LRU 128 |
| [`lvlx128`](../memory/lvlx.md) | `0x10000403` | memory | Load Vector Left Indexed 128 |
| [`lvrx128`](../memory/lvrx.md) | `0x10000443` | memory | Load Vector Right Indexed 128 |
| [`stvlx128`](../memory/stvlx.md) | `0x10000503` | memory | Store Vector Left Indexed 128 |
| [`stvrx128`](../memory/stvrx.md) | `0x10000543` | memory | Store Vector Right Indexed 128 |
| [`lvlxl128`](../memory/lvlxl.md) | `0x10000603` | memory | Load Vector Left Indexed LRU 128 |
| [`lvrxl128`](../memory/lvrxl.md) | `0x10000643` | memory | Load Vector Right Indexed LRU 128 |
| [`stvlxl128`](../memory/stvlxl.md) | `0x10000703` | memory | Store Vector Left Indexed LRU 128 |
| [`stvrxl128`](../memory/stvrxl.md) | `0x10000743` | memory | Store Vector Right Indexed LRU 128 |
<!-- GENERATED: END -->

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# Form `VX128_2` — VX128_2 — VMX128 3-operand arithmetic
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (5) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 23–25 | `VC` | source C 3-bit field |
| 26 | `VA128h` | source A middle bit |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vperm128`](../vmx128/vperm.md) | `0x14000000` | vmx | Vector128 Permute |
<!-- GENERATED: END -->

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# Form `VX128_3` — VX128_3 — VMX128 unary with immediate
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (6) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `IMM` | 5-bit immediate |
| 16–20 | `VB128l` | source B low 5 bits |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vcfpsxws128`](../vmx128/vcfpsxws128.md) | `0x18000230` | vmx | Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate |
| [`vcfpuxws128`](../vmx128/vcfpuxws128.md) | `0x18000270` | vmx | Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate |
| [`vcsxwfp128`](../vmx128/vcsxwfp128.md) | `0x180002b0` | vmx | Vector128 Convert From Signed Fixed-Point Word to Floating-Point |
| [`vcuxwfp128`](../vmx128/vcuxwfp128.md) | `0x180002f0` | vmx | Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point |
| [`vrfim128`](../vmx128/vrfim.md) | `0x18000330` | vmx | Vector128 Round to Floating-Point Integer toward -Infinity |
| [`vrfin128`](../vmx128/vrfin.md) | `0x18000370` | vmx | Vector128 Round to Floating-Point Integer Nearest |
| [`vrfip128`](../vmx128/vrfip.md) | `0x180003b0` | vmx | Vector128 Round to Floating-Point Integer toward +Infinity |
| [`vrfiz128`](../vmx128/vrfiz.md) | `0x180003f0` | vmx | Vector128 Round to Floating-Point Integer toward Zero |
| [`vrefp128`](../vmx128/vrefp.md) | `0x18000630` | vmx | Vector128 Reciprocal Estimate Floating Point |
| [`vrsqrtefp128`](../vmx128/vrsqrtefp.md) | `0x18000670` | vmx | Vector128 Reciprocal Square Root Estimate Floating Point |
| [`vexptefp128`](../vmx128/vexptefp.md) | `0x180006b0` | vmx | Vector128 Log2 Estimate Floating Point |
| [`vlogefp128`](../vmx128/vlogefp.md) | `0x180006f0` | vmx | Vector128 Log2 Estimate Floating Point |
| [`vspltw128`](../vmx128/vspltw.md) | `0x18000730` | vmx | Vector128 Splat Word |
| [`vspltisw128`](../vmx128/vspltisw.md) | `0x18000770` | vmx | Vector128 Splat Immediate Signed Word |
| [`vupkd3d128`](../vmx128/vupkd3d128.md) | `0x180007f0` | vmx | Vector128 Unpack D3Dtype |
<!-- GENERATED: END -->

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# Form `VX128_4` — VX128_4 — VMX128 with sub-opcode selector
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (6) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `IMM` | 5-bit immediate |
| 16–20 | `VB128l` | source B low 5 bits |
| 21–23 | `XO` | extended opcode |
| 24–25 | `z` | sub-operation selector |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vpkd3d128`](../vmx128/vpkd3d128.md) | `0x18000610` | vmx | Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert |
| [`vrlimi128`](../vmx128/vrlimi128.md) | `0x18000710` | vmx | Vector128 Rotate Left Immediate and Mask Insert |
<!-- GENERATED: END -->

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# Form `VX128_5` — VX128_5 — VMX128 with shift field
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22–25 | `SH` | 4-bit shift amount |
| 26 | `VA128h` | source A middle bit |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vsldoi128`](../vmx128/vsldoi.md) | `0x10000010` | vmx | Vector128 Shift Left Double by Octet Immediate |
<!-- GENERATED: END -->

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# Form `VX128_P` — VX128_P — VMX128 permute
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (6) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `PERMl` | permute selector low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21–22 | `—` | reserved |
| 23–25 | `PERMh` | permute selector high 3 bits |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vpermwi128`](../vmx128/vpermwi128.md) | `0x18000210` | vmx | Vector128 Permutate Word Immediate |
<!-- GENERATED: END -->

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# Form `VX128_R` — VX128_R — VMX128 compare (with Rc → CR6)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22–25 | `XO` | extended opcode (compare) |
| 26 | `VA128h` | source A middle bit |
| 27 | `Rc` | record-form flag (updates CR6) |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vcmpeqfp128`](../vmx128/vcmpeqfp.md) | `0x18000000` | vmx | Vector128 Compare Equal-to Floating Point |
| [`vcmpgefp128`](../vmx128/vcmpgefp.md) | `0x18000080` | vmx | Vector128 Compare Greater-Than-or-Equal-to Floating Point |
| [`vcmpgtfp128`](../vmx128/vcmpgtfp.md) | `0x18000100` | vmx | Vector128 Compare Greater-Than Floating-Point |
| [`vcmpbfp128`](../vmx128/vcmpbfp.md) | `0x18000180` | vmx | Vector128 Compare Bounds Floating Point |
| [`vcmpequw128`](../vmx128/vcmpequw.md) | `0x18000200` | vmx | Vector128 Compare Equal-to Unsigned Word |
<!-- GENERATED: END -->

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# Form `X` — X — Extended (10-bit extended opcode)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`cmp`](../alu/cmp.md) | `0x7c000000` | integer | Compare |
| [`tw`](../branch/tw.md) | `0x7c000008` | branch | Trap Word |
| [`lvsl`](../vmx/lvsl.md) | `0x7c00000c` | vmx | Load Vector for Shift Left Indexed |
| [`lvebx`](../memory/lvebx.md) | `0x7c00000e` | memory | Load Vector Element Byte Indexed |
| [`mfcr`](../control/mfcr.md) | `0x7c000026` | control | Move from Condition Register |
| [`lwarx`](../memory/lwarx.md) | `0x7c000028` | memory | Load Word and Reserve Indexed |
| [`ldx`](../memory/ld.md) | `0x7c00002a` | memory | Load Doubleword Indexed |
| [`lwzx`](../memory/lwz.md) | `0x7c00002e` | memory | Load Word and Zero Indexed |
| [`slwx`](../alu/slwx.md) | `0x7c000030` | integer | Shift Left Word |
| [`cntlzwx`](../alu/cntlzwx.md) | `0x7c000034` | integer | Count Leading Zeros Word |
| [`sldx`](../alu/sldx.md) | `0x7c000036` | integer | Shift Left Doubleword |
| [`andx`](../alu/andx.md) | `0x7c000038` | integer | AND |
| [`cmpl`](../alu/cmpl.md) | `0x7c000040` | integer | Compare Logical |
| [`lvsr`](../vmx/lvsr.md) | `0x7c00004c` | vmx | Load Vector for Shift Right Indexed |
| [`lvehx`](../memory/lvehx.md) | `0x7c00004e` | memory | Load Vector Element Half Word Indexed |
| [`ldux`](../memory/ld.md) | `0x7c00006a` | memory | Load Doubleword with Update Indexed |
| [`dcbst`](../memory/dcbst.md) | `0x7c00006c` | memory | Data Cache Block Store |
| [`lwzux`](../memory/lwz.md) | `0x7c00006e` | memory | Load Word and Zero with Update Indexed |
| [`cntlzdx`](../alu/cntlzdx.md) | `0x7c000074` | integer | Count Leading Zeros Doubleword |
| [`andcx`](../alu/andcx.md) | `0x7c000078` | integer | AND with Complement |
| [`td`](../branch/td.md) | `0x7c000088` | branch | Trap Doubleword |
| [`lvewx`](../memory/lvewx.md) | `0x7c00008e` | memory | Load Vector Element Word Indexed |
| [`mfmsr`](../control/mfmsr.md) | `0x7c0000a6` | control | Move from Machine State Register |
| [`ldarx`](../memory/ldarx.md) | `0x7c0000a8` | memory | Load Doubleword and Reserve Indexed |
| [`dcbf`](../memory/dcbf.md) | `0x7c0000ac` | memory | Data Cache Block Flush |
| [`lbzx`](../memory/lbz.md) | `0x7c0000ae` | memory | Load Byte and Zero Indexed |
| [`lvx`](../memory/lvx.md) | `0x7c0000ce` | memory | Load Vector Indexed |
| [`lbzux`](../memory/lbz.md) | `0x7c0000ee` | memory | Load Byte and Zero with Update Indexed |
| [`norx`](../alu/norx.md) | `0x7c0000f8` | integer | NOR |
| [`stvebx`](../memory/stvebx.md) | `0x7c00010e` | memory | Store Vector Element Byte Indexed |
| [`mtmsr`](../control/mtmsr.md) | `0x7c000124` | control | Move to Machine State Register |
| [`stdx`](../memory/std.md) | `0x7c00012a` | memory | Store Doubleword Indexed |
| [`stwcx`](../memory/stwcx.md) | `0x7c00012d` | memory | Store Word Conditional Indexed |
| [`stwx`](../memory/stw.md) | `0x7c00012e` | memory | Store Word Indexed |
| [`stvehx`](../memory/stvehx.md) | `0x7c00014e` | memory | Store Vector Element Half Word Indexed |
| [`mtmsrd`](../control/mtmsrd.md) | `0x7c000164` | control | Move to Machine State Register Doubleword |
| [`stdux`](../memory/std.md) | `0x7c00016a` | memory | Store Doubleword with Update Indexed |
| [`stwux`](../memory/stw.md) | `0x7c00016e` | memory | Store Word with Update Indexed |
| [`stvewx`](../memory/stvewx.md) | `0x7c00018e` | memory | Store Vector Element Word Indexed |
| [`stdcx`](../memory/stdcx.md) | `0x7c0001ad` | memory | Store Doubleword Conditional Indexed |
| [`stbx`](../memory/stb.md) | `0x7c0001ae` | memory | Store Byte Indexed |
| [`stvx`](../memory/stvx.md) | `0x7c0001ce` | memory | Store Vector Indexed |
| [`dcbtst`](../memory/dcbtst.md) | `0x7c0001ec` | memory | Data Cache Block Touch for Store |
| [`stbux`](../memory/stb.md) | `0x7c0001ee` | memory | Store Byte with Update Indexed |
| [`dcbt`](../memory/dcbt.md) | `0x7c00022c` | memory | Data Cache Block Touch |
| [`lhzx`](../memory/lhz.md) | `0x7c00022e` | memory | Load Half Word and Zero Indexed |
| [`eqvx`](../alu/eqvx.md) | `0x7c000238` | integer | Equivalent |
| [`lhzux`](../memory/lhz.md) | `0x7c00026e` | memory | Load Half Word and Zero with Update Indexed |
| [`xorx`](../alu/xorx.md) | `0x7c000278` | integer | XOR |
| [`lwax`](../memory/lwa.md) | `0x7c0002aa` | memory | Load Word Algebraic Indexed |
| [`lhax`](../memory/lha.md) | `0x7c0002ae` | memory | Load Half Word Algebraic Indexed |
| [`lvxl`](../memory/lvxl.md) | `0x7c0002ce` | memory | Load Vector Indexed LRU |
| [`lwaux`](../memory/lwa.md) | `0x7c0002ea` | memory | Load Word Algebraic with Update Indexed |
| [`lhaux`](../memory/lha.md) | `0x7c0002ee` | memory | Load Half Word Algebraic with Update Indexed |
| [`sthx`](../memory/sth.md) | `0x7c00032e` | memory | Store Half Word Indexed |
| [`orcx`](../alu/orcx.md) | `0x7c000338` | integer | OR with Complement |
| [`sthux`](../memory/sth.md) | `0x7c00036e` | memory | Store Half Word with Update Indexed |
| [`orx`](../alu/orx.md) | `0x7c000378` | integer | OR |
| [`dcbi`](../memory/dcbi.md) | `0x7c0003ac` | memory | Data Cache Block Invalidate |
| [`nandx`](../alu/nandx.md) | `0x7c0003b8` | integer | NAND |
| [`stvxl`](../memory/stvxl.md) | `0x7c0003ce` | memory | Store Vector Indexed LRU |
| [`mcrxr`](../control/mcrxr.md) | `0x7c000400` | control | Move to Condition Register from XER |
| [`lvlx`](../memory/lvlx.md) | `0x7c00040e` | memory | Load Vector Left Indexed |
| [`ldbrx`](../memory/ldbrx.md) | `0x7c000428` | memory | Load Doubleword Byte-Reverse Indexed |
| [`lswx`](../memory/lswx.md) | `0x7c00042a` | memory | Load String Word Indexed |
| [`lwbrx`](../memory/lwbrx.md) | `0x7c00042c` | memory | Load Word Byte-Reverse Indexed |
| [`lfsx`](../memory/lfs.md) | `0x7c00042e` | memory | Load Floating-Point Single Indexed |
| [`srwx`](../alu/srwx.md) | `0x7c000430` | integer | Shift Right Word |
| [`srdx`](../alu/srdx.md) | `0x7c000436` | integer | Shift Right Doubleword |
| [`lvrx`](../memory/lvrx.md) | `0x7c00044e` | memory | Load Vector Right Indexed |
| [`lfsux`](../memory/lfs.md) | `0x7c00046e` | memory | Load Floating-Point Single with Update Indexed |
| [`lswi`](../memory/lswi.md) | `0x7c0004aa` | memory | Load String Word Immediate |
| [`sync`](../alu/sync.md) | `0x7c0004ac` | integer | Synchronize |
| [`lfdx`](../memory/lfd.md) | `0x7c0004ae` | memory | Load Floating-Point Double Indexed |
| [`lfdux`](../memory/lfd.md) | `0x7c0004ee` | memory | Load Floating-Point Double with Update Indexed |
| [`stvlx`](../memory/stvlx.md) | `0x7c00050e` | memory | Store Vector Left Indexed |
| [`stdbrx`](../memory/stdbrx.md) | `0x7c000528` | memory | Store Doubleword Byte-Reverse Indexed |
| [`stswx`](../memory/stswx.md) | `0x7c00052a` | memory | Store String Word Indexed |
| [`stwbrx`](../memory/stwbrx.md) | `0x7c00052c` | memory | Store Word Byte-Reverse Indexed |
| [`stfsx`](../memory/stfs.md) | `0x7c00052e` | memory | Store Floating-Point Single Indexed |
| [`stvrx`](../memory/stvrx.md) | `0x7c00054e` | memory | Store Vector Right Indexed |
| [`stfsux`](../memory/stfs.md) | `0x7c00056e` | memory | Store Floating-Point Single with Update Indexed |
| [`stswi`](../memory/stswi.md) | `0x7c0005aa` | memory | Store String Word Immediate |
| [`stfdx`](../memory/stfd.md) | `0x7c0005ae` | memory | Store Floating-Point Double Indexed |
| [`stfdux`](../memory/stfd.md) | `0x7c0005ee` | memory | Store Floating-Point Double with Update Indexed |
| [`lvlxl`](../memory/lvlxl.md) | `0x7c00060e` | memory | Load Vector Left Indexed LRU |
| [`lhbrx`](../memory/lhbrx.md) | `0x7c00062c` | memory | Load Half Word Byte-Reverse Indexed |
| [`srawx`](../alu/srawx.md) | `0x7c000630` | integer | Shift Right Algebraic Word |
| [`sradx`](../alu/sradx.md) | `0x7c000634` | integer | Shift Right Algebraic Doubleword |
| [`lvrxl`](../memory/lvrxl.md) | `0x7c00064e` | memory | Load Vector Right Indexed LRU |
| [`srawix`](../alu/srawix.md) | `0x7c000670` | integer | Shift Right Algebraic Word Immediate |
| [`eieio`](../alu/eieio.md) | `0x7c0006ac` | integer | Enforce In-Order Execution of I/O |
| [`stvlxl`](../memory/stvlxl.md) | `0x7c00070e` | memory | Store Vector Left Indexed LRU |
| [`sthbrx`](../memory/sthbrx.md) | `0x7c00072c` | memory | Store Half Word Byte-Reverse Indexed |
| [`extshx`](../alu/extshx.md) | `0x7c000734` | integer | Extend Sign Half Word |
| [`stvrxl`](../memory/stvrxl.md) | `0x7c00074e` | memory | Store Vector Right Indexed LRU |
| [`extsbx`](../alu/extsbx.md) | `0x7c000774` | integer | Extend Sign Byte |
| [`icbi`](../memory/icbi.md) | `0x7c0007ac` | memory | Instruction Cache Block Invalidate |
| [`stfiwx`](../memory/stfiwx.md) | `0x7c0007ae` | memory | Store Floating-Point as Integer Word Indexed |
| [`extswx`](../alu/extswx.md) | `0x7c0007b4` | integer | Extend Sign Word |
| [`fcmpu`](../fpu/fcmpu.md) | `0xfc000000` | fpu | Floating Compare Unordered |
| [`frspx`](../fpu/frspx.md) | `0xfc000018` | fpu | Floating Round to Single |
| [`fctiwx`](../fpu/fctiwx.md) | `0xfc00001c` | fpu | Floating Convert to Integer Word |
| [`fctiwzx`](../fpu/fctiwzx.md) | `0xfc00001e` | fpu | Floating Convert to Integer Word with Round Toward Zero |
| [`fcmpo`](../fpu/fcmpo.md) | `0xfc000040` | fpu | Floating Compare Ordered |
| [`mtfsb1x`](../control/mtfsb1x.md) | `0xfc00004c` | control | Move to FPSCR Bit 1 |
| [`fnegx`](../fpu/fnegx.md) | `0xfc000050` | fpu | Floating Negate |
| [`mcrfs`](../control/mcrfs.md) | `0xfc000080` | control | Move to Condition Register from FPSCR |
| [`mtfsb0x`](../control/mtfsb0x.md) | `0xfc00008c` | control | Move to FPSCR Bit 0 |
| [`fmrx`](../fpu/fmrx.md) | `0xfc000090` | fpu | Floating Move Register |
| [`mtfsfix`](../control/mtfsfix.md) | `0xfc00010c` | control | Move to FPSCR Field Immediate |
| [`fnabsx`](../fpu/fnabsx.md) | `0xfc000110` | fpu | Floating Negative Absolute Value |
| [`fabsx`](../fpu/fabsx.md) | `0xfc000210` | fpu | Floating Absolute Value |
| [`mffsx`](../control/mffsx.md) | `0xfc00048e` | control | Move from FPSCR |
| [`fctidx`](../fpu/fctidx.md) | `0xfc00065c` | fpu | Floating Convert to Integer Doubleword |
| [`fctidzx`](../fpu/fctidzx.md) | `0xfc00065e` | fpu | Floating Convert to Integer Doubleword with Round Toward Zero |
| [`fcfidx`](../fpu/fcfidx.md) | `0xfc00069c` | fpu | Floating Convert From Integer Doubleword |
<!-- GENERATED: END -->

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# Form `XFL` — XFL — Floating Fields (mtfsf)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (63) |
| 6 | `L` | field-select behaviour |
| 7–14 | `FM` | FPSCR field mask |
| 15 | `W` | immediate-value flag |
| 16–20 | `FRB` | source FPR |
| 21–30 | `XO` | extended opcode |
| 31 | `Rc` | record-form flag (updates CR1) |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`mtfsfx`](../control/mtfsfx.md) | `0xfc00058e` | control | Move to FPSCR Fields |
<!-- GENERATED: END -->

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# Form `XFX` — XFX — Fixed (SPR/TBR/CR-field access)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (31) |
| 6–10 | `RT` | destination / source GPR |
| 11–20 | `spr/tbr/FXM` | SPR/TBR number (byte-swapped halves) or CR field mask |
| 21–30 | `XO` | extended opcode |
| 31 | `—` | reserved |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`mtcrf`](../control/mtcrf.md) | `0x7c000120` | control | Move to Condition Register Fields |
| [`mfspr`](../control/mfspr.md) | `0x7c0002a6` | control | Move from Special-Purpose Register |
| [`mftb`](../control/mftb.md) | `0x7c0002e6` | control | Move from Time Base |
| [`mtspr`](../control/mtspr.md) | `0x7c0003a6` | control | Move to Special-Purpose Register |
<!-- GENERATED: END -->

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# Form `XL` — XL — Extended, Link (branch-to-LR/CTR, CR logical)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (19) |
| 6–10 | `BT/BO` | target / branch options |
| 11–15 | `BA/BI` | source A / CR bit to test |
| 16–20 | `BB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `LK` | link flag |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`mcrf`](../control/mcrf.md) | `0x4c000000` | control | Move Condition Register Field |
| [`bclrx`](../branch/bclrx.md) | `0x4c000020` | branch | Branch Conditional to Link Register |
| [`crnor`](../control/crnor.md) | `0x4c000042` | control | Condition Register NOR |
| [`crandc`](../control/crandc.md) | `0x4c000102` | control | Condition Register AND with Complement |
| [`isync`](../alu/isync.md) | `0x4c00012c` | integer | Instruction Synchronize |
| [`crxor`](../control/crxor.md) | `0x4c000182` | control | Condition Register XOR |
| [`crnand`](../control/crnand.md) | `0x4c0001c2` | control | Condition Register NAND |
| [`crand`](../control/crand.md) | `0x4c000202` | control | Condition Register AND |
| [`creqv`](../control/creqv.md) | `0x4c000242` | control | Condition Register Equivalent |
| [`crorc`](../control/crorc.md) | `0x4c000342` | control | Condition Register OR with Complement |
| [`cror`](../control/cror.md) | `0x4c000382` | control | Condition Register OR |
| [`bcctrx`](../branch/bcctrx.md) | `0x4c000420` | branch | Branch Conditional to Count Register |
<!-- GENERATED: END -->

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# Form `XO` — XO — Extended, Overflow (ALU with OE/Rc)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (31) |
| 6–10 | `RT` | destination GPR |
| 11–15 | `RA` | source A |
| 16–20 | `RB` | source B |
| 21 | `OE` | overflow-enable flag |
| 22–30 | `XO` | extended opcode (9 bits) |
| 31 | `Rc` | record-form flag |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`subfcx`](../alu/subfcx.md) | `0x7c000010` | integer | Subtract From Carrying |
| [`mulhdux`](../alu/mulhdux.md) | `0x7c000012` | integer | Multiply High Doubleword Unsigned |
| [`addcx`](../alu/addcx.md) | `0x7c000014` | integer | Add Carrying |
| [`mulhwux`](../alu/mulhwux.md) | `0x7c000016` | integer | Multiply High Word Unsigned |
| [`subfx`](../alu/subfx.md) | `0x7c000050` | integer | Subtract From |
| [`mulhdx`](../alu/mulhdx.md) | `0x7c000092` | integer | Multiply High Doubleword |
| [`mulhwx`](../alu/mulhwx.md) | `0x7c000096` | integer | Multiply High Word |
| [`negx`](../alu/negx.md) | `0x7c0000d0` | integer | Negate |
| [`subfex`](../alu/subfex.md) | `0x7c000110` | integer | Subtract From Extended |
| [`addex`](../alu/addex.md) | `0x7c000114` | integer | Add Extended |
| [`subfzex`](../alu/subfzex.md) | `0x7c000190` | integer | Subtract From Zero Extended |
| [`addzex`](../alu/addzex.md) | `0x7c000194` | integer | Add to Zero Extended |
| [`subfmex`](../alu/subfmex.md) | `0x7c0001d0` | integer | Subtract From Minus One Extended |
| [`mulldx`](../alu/mulldx.md) | `0x7c0001d2` | integer | Multiply Low Doubleword |
| [`addmex`](../alu/addmex.md) | `0x7c0001d4` | integer | Add to Minus One Extended |
| [`mullwx`](../alu/mullwx.md) | `0x7c0001d6` | integer | Multiply Low Word |
| [`addx`](../alu/addx.md) | `0x7c000214` | integer | Add |
| [`divdux`](../alu/divdux.md) | `0x7c000392` | integer | Divide Doubleword Unsigned |
| [`divwux`](../alu/divwux.md) | `0x7c000396` | integer | Divide Word Unsigned |
| [`divdx`](../alu/divdx.md) | `0x7c0003d2` | integer | Divide Doubleword |
| [`divwx`](../alu/divwx.md) | `0x7c0003d6` | integer | Divide Word |
<!-- GENERATED: END -->

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# Form `XS` — XS — Extended, Shift (64-bit sradi)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (31) |
| 6–10 | `RS` | source GPR |
| 11–15 | `RA` | destination GPR |
| 16–20 | `sh` | shift amount low 5 bits |
| 21–29 | `XO` | extended opcode (9 bits) |
| 30 | `sh5` | shift amount high bit |
| 31 | `Rc` | record-form flag |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`sradix`](../alu/sradix.md) | `0x7c000674` | integer | Shift Right Algebraic Doubleword Immediate |
<!-- GENERATED: END -->