Files

MechaCat02 e6d43a23ac chore: add migration/ bundle for cross-machine setup

Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

2026-05-10 21:38:38 +02:00

4.0 KiB

Raw Blame History

Form `VX128` — VX128 — VMX128 3-operand (register-fused)

Bit Layout

Bits	Field	Meaning
0–5	`OPCD`	primary opcode (4 or 5)
6–10	`VD128l`	destination low 5 bits
11–15	`VA128l`	source A low 5 bits
16–20	`VB128l`	source B low 5 bits
21	`VA128H`	source A high bit
22	`—`	reserved
23–25	`VC`	optional VC / XO sub-field
26	`VA128h`	source A middle bit
27	`—`	reserved
28–29	`VD128h`	destination high 2 bits
30–31	`VB128h`	source B high 2 bits

Instructions Using This Form

Mnemonic	Opcode	Group	Description
`vaddfp128`	`0x14000010`	vmx	Vector128 Add Floating Point
`vsubfp128`	`0x14000050`	vmx	Vector128 Subtract Floating Point
`vmulfp128`	`0x14000090`	vmx	Vector128 Multiply Floating-Point
`vmaddfp128`	`0x140000d0`	vmx	Vector128 Multiply Add Floating Point
`vmaddcfp128`	`0x14000110`	vmx	Vector128 Multiply Add Floating Point
`vnmsubfp128`	`0x14000150`	vmx	Vector128 Negative Multiply-Subtract Floating Point
`vmsum3fp128`	`0x14000190`	vmx	Vector128 Multiply Sum 3-way Floating Point
`vmsum4fp128`	`0x140001d0`	vmx	Vector128 Multiply Sum 4-way Floating-Point
`vpkshss128`	`0x14000200`	vmx	Vector128 Pack Signed Half Word Signed Saturate
`vand128`	`0x14000210`	vmx	Vector128 Logical AND
`vpkshus128`	`0x14000240`	vmx	Vector128 Pack Signed Half Word Unsigned Saturate
`vandc128`	`0x14000250`	vmx	Vector128 Logical AND with Complement
`vpkswss128`	`0x14000280`	vmx	Vector128 Pack Signed Word Signed Saturate
`vnor128`	`0x14000290`	vmx	Vector128 Logical NOR
`vpkswus128`	`0x140002c0`	vmx	Vector128 Pack Signed Word Unsigned Saturate
`vor128`	`0x140002d0`	vmx	Vector128 Logical OR
`vpkuhum128`	`0x14000300`	vmx	Vector128 Pack Unsigned Half Word Unsigned Modulo
`vxor128`	`0x14000310`	vmx	Vector128 Logical XOR
`vpkuhus128`	`0x14000340`	vmx	Vector128 Pack Unsigned Half Word Unsigned Saturate
`vsel128`	`0x14000350`	vmx	Vector128 Conditional Select
`vpkuwum128`	`0x14000380`	vmx	Vector128 Pack Unsigned Word Unsigned Modulo
`vslo128`	`0x14000390`	vmx	Vector128 Shift Left Octet
`vpkuwus128`	`0x140003c0`	vmx	Vector128 Pack Unsigned Word Unsigned Saturate
`vsro128`	`0x140003d0`	vmx	Vector128 Shift Right Octet
`vrlw128`	`0x18000050`	vmx	Vector128 Rotate Left Word
`vslw128`	`0x180000d0`	vmx	Vector128 Shift Left Integer Word
`vsraw128`	`0x18000150`	vmx	Vector128 Shift Right Arithmetic Word
`vsrw128`	`0x180001d0`	vmx	Vector128 Shift Right Word
`vmaxfp128`	`0x18000280`	vmx	Vector128 Maximum Floating Point
`vminfp128`	`0x180002c0`	vmx	Vector128 Minimum Floating Point
`vmrghw128`	`0x18000300`	vmx	Vector128 Merge High Word
`vmrglw128`	`0x18000340`	vmx	Vector128 Merge Low Word
`vupkhsb128`	`0x18000380`	vmx	Vector128 Unpack High Signed Byte
`vupklsb128`	`0x180003c0`	vmx	Vector128 Unpack Low Signed Byte

4.0 KiB Raw Blame History Unescape Escape

Form VX128 — VX128 — VMX128 3-operand (register-fused)

Bit Layout

Instructions Using This Form

4.0 KiB

Raw Blame History

Form `VX128` — VX128 — VMX128 3-operand (register-fused)